SystemC 2.2.0 --- May  7 2008 14:48:18
        Copyright (c) 1996-2006 by all Contributors
                    ALL RIGHTS RESERVED

 - CLUSTER_X    = 1
 - CLUSTER_Y    = 1
 - NB_PROCS_MAX = 4
 - NB_DMAS_MAX  = 1
 - NB_TTYS      = 8
 - NB_NICS      = 8
 - MEMC_WAYS    = 16
 - MEMC_SETS    = 256
 - RAM_LATENCY  = 0
 - MAX_FROZEN   = 10000

Mapping table: ad:(0,16) id:(0,14) cacheability mask: 0xff0000
 <Segment "d_seg_memc_0_0": base = 0 / size = 0xc00000 / tgtid = (0,0) / cached>
 <Segment "d_seg_xicu_0_0": base = 0xf00000 / size = 0x1000 / tgtid = (0,1) / uncached>
 <Segment "d_seg_mdma_0_0": base = 0xf30000 / size = 0x1000 / tgtid = (0,2) / uncached>
 <Segment "d_seg_mtty": base = 0xbff20000 / size = 0x1000 / tgtid = (0,3) / uncached>
 <Segment "d_seg_fbuf": base = 0xbfd00000 / size = 0x200000 / tgtid = (0,4) / uncached>
 <Segment "d_seg_bdev": base = 0xbff10000 / size = 0x1000 / tgtid = (0,6) / uncached>
 <Segment "d_seg_mnic": base = 0xbff80000 / size = 0x12000 / tgtid = (0,7) / uncached>
 <Segment "d_seg_brom": base = 0xbfc00000 / size = 0x100000 / tgtid = (0,5) / cached>

Mapping table: ad:(0,14) id:(0,14) cacheability mask: 0xff0000
 <Segment "c_seg_memc_0_0": base = 0x100000 / size = 0x10 / tgtid = (0,4) / uncached>
 <Segment "c_seg_proc_0_0_0": base = 0 / size = 0x10 / tgtid = (0,0) / uncached>
 <Segment "c_seg_proc_0_0_1": base = 0x40000 / size = 0x10 / tgtid = (0,1) / uncached>
 <Segment "c_seg_proc_0_0_2": base = 0x80000 / size = 0x10 / tgtid = (0,2) / uncached>
 <Segment "c_seg_proc_0_0_3": base = 0xc0000 / size = 0x10 / tgtid = (0,3) / uncached>

Mapping table: ad:(1) id:(0) cacheability mask: 0xf0000000
 <Segment "x_seg_memc_0_0": base = 0 / size = 0xc00000 / tgtid = (0) / uncached>

  - building proc_0_0-*
[GDB] SOCLIB_GDB env variable may contain the following flag letters: 
  X (dont break on except),      S (wait connect on except),  F (start frozen)
  C (functions branch trace),    Z (functions entry trace),   D (gdb protocol debug),
  W (dont break on watchpoints), T (exit sumilation on trap), E (exit on fault)
  => See http://www.soclib.fr/trac/dev/wiki/Tools/GdbServer
[GDB] listening on port 2346
  - building memc_0_0
  - building xram_0_0
  - building xicu_0_0
  - building dma_0_0
  - building xbard_0_0
  - building ringc_0_0
  - building wrappers in cluster_0_0
  - building cmdrouter_0_0
  - building rsprouter_0_0
  - building brom
  - building fbuf
Frame buffer: 128 128 420 /tmp/fbuf.raw6nd3zY
  - building fbuf

Info: (I804) /IEEE_Std_1666/deprecated: sc_sensitive_pos is deprecated use sc_sensitive << with pos() instead

Info: (I804) /IEEE_Std_1666/deprecated: sc_sensitive_neg is deprecated use sc_sensitive << with neg() instead
  - building mnic
ERROR in RX_GMII : cannot open file giet_vm/nic/rx_data.txt
ERROR in TX_GMII : cannot open file giet_vm/nic/tx_data.txt
  - building mtty

  - CMD & RSP routers connected
  - VCI/DSPIN wrappers connected
  - Direct crossbar connected
  - Coherence ring connected
  - Processors connected
  - XICU connected
  - MEMC connected
  - XRAM connected
  - MDMA connected
  - BDEV connected
  - FBUF connected
  - MNIC connected
  - BROM connected
  - MTTY connected
cluster_0_0 constructed

Horizontal connections established
Vertical connections established
Loading at 0 size 12582912: kernel_code kernel_data kernel_unc kernel_init data code data code data code data code 
Loading at 0xbfc00000 size 1048576: boot_code boot_mapping 
****************** cycle 1701001 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00594>
  <InsRsp    valid no error ins 0x1bdb42>
  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc04f84 wdata 0 be 0xf>
  <DataRsp   valid no error rdata 0x12000>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_TLB_PTE2_GET> MISS in dcache: PTE address = 0x000019480
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701002 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00594>
  <InsRsp    valid no error ins 0x1bdb42>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc04f84 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_WRITE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_MISS_SELECT> Select a slot: / WAY = 1 / SET = 18 / PADDR = 0x000019480 / VICTIM = 0x000002ed2
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_WRITE> Add an entry in the heap: owner_id = 1 owner_ins = 0
****************** cycle 1701003 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc00598>
  <InsRsp    valid no error ins 0x489b0000>
  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc04f84 wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_MISS_CLEAN> Switch to ZOMBI state / way = 1 / set = 18
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 2
****************** cycle 1701004 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc0059c>
  <InsRsp    valid no error ins 0x241b000f>
  <DataReq   valid mode MODE_KERNEL type XTN_WRITE (XTN_PTPR) wdata 0x9 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_XTN_SWITCH | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_dcache_cc_send_nline = 0x000002ed2
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 2
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d0 / for address 0x000019480
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 3
****************** cycle 1701005 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc0059c>
  <InsRsp  invalid no error ins 0>
  <DataReq   valid mode MODE_KERNEL type XTN_WRITE (XTN_PTPR) wdata 0x9 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_XTN_TLB_FLUSH | DCACHE_XTN_SWITCH | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_READ | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_dcache_cc_send_nline = 0x000002ed2
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 3
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_READ> Push into read_fifo: address = 0x000019480 srcid = 0d0 trdid = 0d0 pktid = 0d1 plen = 0d64
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 4
****************** cycle 1701006 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc0059c>
  <InsRsp  invalid no error ins 0>
  <DataReq   valid mode MODE_KERNEL type XTN_WRITE (XTN_PTPR) wdata 0x9 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_XTN_SWITCH | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 4
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 5
****************** cycle 1701007 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc0059c>
  <InsRsp    valid no error ins 0x241b000f>
  <DataReq   valid mode MODE_KERNEL type XTN_WRITE (XTN_PTPR) wdata 0x9 be 0xf>
  <DataRsp   valid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_CLEANUP | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 6
****************** cycle 1701008 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a0>
  <InsRsp    valid no error ins 0x489b0800>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_PTPR) wdata 0x9 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_CLEANUP | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 6
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CLEANUP_IDLE> Cleanup request: / owner_id = 0 / owner_ins = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 7
****************** cycle 1701009 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a4>
  <InsRsp    valid no error ins 0x3c1a8009>
  <DataReq   valid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp   valid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_GET_NLINE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 7
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CLEANUP_GET_NLINE> Cleanup request: / address = 0xbb480
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 8
****************** cycle 1701010 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 8
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 9
****************** cycle 1701011 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_TLB_MISS | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2.DCACHE_TLB_MISS> ITLB miss / VADDR = 0xbfc005a8 / BYPASS = 0 / PTE_ADR = 0x0000137f8
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 9
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CLEANUP_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 10
****************** cycle 1701012 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_TLB_PTE1_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_DIR_LOCK
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2.DCACHE_TLB_PTE1_GET> MISS in dcache: PTE1 address = 0x0000137f8
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 10
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CLEANUP_DIR_LOCK> Test directory status:  line = 0x000000bb480 / hit = 0x1 / dir_id = 0 / dir_ins = 0 / search_id = 0 / search_ins = 0 / count = 0x1 / is_cnt = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 11
****************** cycle 1701013 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_SELECT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_DIR_WRITE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_SELECT> Select a slot: / WAY = 0 / SET = 31 / PADDR = 0x0000137f8
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 11
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CLEANUP_DIR_WRITE> Update directory: address = 0xbb480 / dir_id = 0 / dir_ins = 0 / count = 0 / is_cnt = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 12
****************** cycle 1701014 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_DATA_MISS | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_SEND_ACK
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 12
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CLEANUP_SEND_ACK> Send the response to a cleanup request: srcid = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 13
****************** cycle 1701015 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_DATA_MISS | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 13
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d2 / for address 0x0000137c0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0xc0000018 / cpt = 14
****************** cycle 1701016 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_DATA_MISS | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_READ | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_ACK | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xc0000018 / WAY = 0 / SET = 31 / WORD = 14
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_READ> Push into read_fifo: address = 0x0000137c0 srcid = 0d2 trdid = 0d0 pktid = 0d1 plen = 0d64
  <MEMC memc_0_0.CC_SEND_CLEANUP_ACK> Cleanup Acknowledgement for srcid 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0xc000001a / cpt = 15
****************** cycle 1701017 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xc000001a / WAY = 0 / SET = 31 / WORD = 15
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_RSP> Request the TGT_RSP FSM to return data: rsrcid = 1 / address = 0x137c0 / nwords = 16
****************** cycle 1701018 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DIR_UPDT> Switch slot to VALID state PADDR = 0x0000137f8 / WAY = 0 / SET = 31
1 | way 0 | set 0 | @ 0xbfc0c000 | 0xbabef00d | 0x1 | 0x1 | 0x1 | 0xf | 0x4 | 0 | 0 | 0 | 0 | 0xb | 0x24 | 0x25 | 0x7 | 0x4 | 0x1c
0 | way 0 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 31 | @ 0x137c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xc0000018 | 0xc000001a
0 | way 0 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 62 | @ 0xbfc04f80 | 0x3000 | 0x12000 | 0x68000 | 0x8e000 | 0xb4000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 0 | @ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 0 | @ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 0 | @ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_IDLE> Read request: srcid = 0 / address = 0x19480 / pktid = 0x1 / nwords = 16
****************** cycle 1701019 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE1_GET> HIT in dcache / paddr = 0x0000137f8 / way = 0 / set = 31 / word = 14 / PTD = 0xc0000018
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
****************** cycle 1701020 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_GET> MISS in dcache: PTE address = 0x000018000
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
****************** cycle 1701021 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_CC_CHECK> paddr = 0x0000ba040 r_dcache_vci_paddr = 0x000019480 mask = 0x0ffffffc0 (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) = 0x1 (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT) = 0 ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) = 0
  <PROC proc_0_0_0 DCACHE_CC_CHECK> CC_TYPE_CLACK Switch slot to EMPTY state set = 0x12 / way = 0x1
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_SELECT> Select a slot: / WAY = 1 / SET = 0 / PADDR = 0x000018000
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_LOCK> Accessing directory:  address = 0x19480 / hit = 1 / count = 0 / is_cnt = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 0
****************** cycle 1701022 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_HIT | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_HIT> Update directory entry: addr = 0x19480 / set = 82 / way = 0 / owner_id = 0 / owner_ins = 0 / count = 1 / is_cnt = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 1
****************** cycle 1701023 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000018000
****************** cycle 1701024 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_READ | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 1
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_READ> Push into read_fifo: address = 0x000018000 srcid = 0d3 trdid = 0d0 pktid = 0d1 plen = 0d64
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 2
****************** cycle 1701025 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 2
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 3
****************** cycle 1701026 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 3
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 4
****************** cycle 1701027 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 4
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 5
****************** cycle 1701028 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 5
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 6
****************** cycle 1701029 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 6
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 7
****************** cycle 1701030 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 7
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 8
****************** cycle 1701031 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 8
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 9
****************** cycle 1701032 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 9
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 10
****************** cycle 1701033 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 10
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 11
****************** cycle 1701034 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 11
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 12
****************** cycle 1701035 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 12
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 13
****************** cycle 1701036 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 13
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0xc0000018 / cpt = 14
****************** cycle 1701037 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xc0000018 / WAY = 0 / SET = 31 / WORD = 14
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0xc000001a / cpt = 15
****************** cycle 1701038 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xc000001a / WAY = 0 / SET = 31 / WORD = 15
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_RSP> Request the TGT_RSP FSM to return data: rsrcid = 0 / address = 0x19480 / nwords = 16
****************** cycle 1701039 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DIR_UPDT> Switch slot to VALID state PADDR = 0x0000137f8 / WAY = 0 / SET = 31
1 | way 0 | set 0 | @ 0xbfc0c000 | 0xbabef00d | 0x1 | 0x1 | 0x1 | 0xf | 0x4 | 0 | 0 | 0 | 0 | 0xb | 0x24 | 0x25 | 0x7 | 0x4 | 0x1c
0 | way 0 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 31 | @ 0x137c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xc0000018 | 0xc000001a
0 | way 0 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 61 | @ 0xbfc04f40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x1000 | 0x2000
1 | way 0 | set 62 | @ 0xbfc04f80 | 0x3000 | 0x12000 | 0x68000 | 0x8e000 | 0xb4000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 0 | @ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 0 | @ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 0 | @ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_IDLE> Read request: srcid = 2 / address = 0x137c0 / pktid = 0x1 / nwords = 16
****************** cycle 1701040 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1.DCACHE_TLB_PTE1_GET> HIT in dcache / paddr = 0x0000137f8 / way = 0 / set = 31 / word = 14 / PTD = 0xc0000018
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
****************** cycle 1701041 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_TLB_PTE2_GET> MISS in dcache: PTE address = 0x000018000
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_LOCK> Accessing directory:  address = 0x137c0 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1701042 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_SELECT> Select a slot: / WAY = 1 / SET = 0 / PADDR = 0x000018000
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_REQ> Requesting HEAP lock 
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0x8a000000 / cpt = 0
****************** cycle 1701043 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_LOCK> Update directory: tag = 0x4 set = 223 way = 0 count = 4 is_cnt = 1
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0xd / cpt = 1
****************** cycle 1701044 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_ERASE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x8a000000 / WAY = 1 / SET = 18 / WORD = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d1 / for address 0x000018000
****************** cycle 1701045 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_READ | TGT_RSP_READ | READ_HEAP_LAST | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xd / WAY = 1 / SET = 18 / WORD = 1
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_READ> Push into read_fifo: address = 0x000018000 srcid = 0d1 trdid = 0d0 pktid = 0d1 plen = 0d64
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 2
****************** cycle 1701046 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 1 / SET = 18 / WORD = 2
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 3
****************** cycle 1701047 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 1 / SET = 18 / WORD = 3
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 4
****************** cycle 1701048 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 1 / SET = 18 / WORD = 4
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 5
****************** cycle 1701049 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 1 / SET = 18 / WORD = 5
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 6
****************** cycle 1701050 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 1 / SET = 18 / WORD = 6
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 7
****************** cycle 1701051 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 1 / SET = 18 / WORD = 7
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 8
****************** cycle 1701052 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 1 / SET = 18 / WORD = 8
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 9
****************** cycle 1701053 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 1 / SET = 18 / WORD = 9
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 10
****************** cycle 1701054 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 1 / SET = 18 / WORD = 10
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 11
****************** cycle 1701055 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 1 / SET = 18 / WORD = 11
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 12
****************** cycle 1701056 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 1 / SET = 18 / WORD = 12
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 13
****************** cycle 1701057 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 1 / SET = 18 / WORD = 13
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 14
****************** cycle 1701058 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 1 / SET = 18 / WORD = 14
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 15
****************** cycle 1701059 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 1 / SET = 18 / WORD = 15
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_RSP> Request the TGT_RSP FSM to return data: rsrcid = 2 / address = 0x137c0 / nwords = 16
****************** cycle 1701060 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DIR_UPDT> Switch slot to VALID state PADDR = 0x000019480 / WAY = 1 / SET = 18
1 | way 0 | set 0 | @ 0x13000 | 0xc0000019 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 1 | @ 0x94040 | 0x8c000000 | 0xbfc08 | 0x8c000000 | 0xbfc09 | 0xac400000 | 0xbfc0a | 0x8c000000 | 0xbfc0b | 0xac000000 | 0xbfc0c | 0xac000000 | 0xbfc0d | 0x8c000000 | 0xbfc0e | 0 | 0
1 | way 0 | set 2 | @ 0xbfc0c080 | 0 | 0x6 | 0 | 0x47455350 | 0x4d41525f | 0 | 0 | 0 | 0 | 0 | 0x75000000 | 0 | 0xc00000 | 0 | 0 | 0xd6000
1 | way 0 | set 3 | @ 0xbfc0e0c0 | 0x12 | 0x2 | 0x2 | 0 | 0x13 | 0x2 | 0x3 | 0 | 0x14 | 0x2 | 0x4 | 0 | 0x15 | 0x2 | 0x5 | 0
1 | way 0 | set 4 | @ 0xbfc0e100 | 0x16 | 0x2 | 0x6 | 0 | 0x17 | 0x2 | 0x7 | 0 | 0x18 | 0x2 | 0x8 | 0 | 0x19 | 0x2 | 0x9 | 0
1 | way 0 | set 5 | @ 0xbfc0c140 | 0 | 0 | 0xf00000 | 0x1000 | 0x2 | 0 | 0xf00000 | 0x47455350 | 0x434f495f | 0 | 0 | 0 | 0 | 0 | 0 | 0xbff10000
1 | way 0 | set 6 | @ 0xbfc0e180 | 0x1e | 0x2 | 0xe | 0 | 0x1f | 0x4 | 0 | 0x1 | 0x1 | 0x1 | 0 | 0x1 | 0x2 | 0x1 | 0 | 0x1
1 | way 0 | set 7 | @ 0xbc1c0 | 0x84000000 | 0xbfe38 | 0x84000000 | 0xbfe39 | 0x84000000 | 0xbfe3a | 0x84000000 | 0xbfe3b | 0x84000000 | 0xbfe3c | 0x84000000 | 0xbfe3d | 0x84000000 | 0xbfe3e | 0x84000000 | 0xbfe3f
1 | way 0 | set 8 | @ 0xbfc0c200 | 0 | 0 | 0 | 0 | 0 | 0 | 0xbff80000 | 0x21000 | 0x2 | 0 | 0xbff80000 | 0x47455350 | 0x4443475f | 0 | 0 | 0
1 | way 0 | set 9 | @ 0x6e240 | 0x84000000 | 0xbfe48 | 0x84000000 | 0xbfe49 | 0x84000000 | 0xbfe4a | 0x84000000 | 0xbfe4b | 0x84000000 | 0xbfe4c | 0x84000000 | 0xbfe4d | 0x84000000 | 0xbfe4e | 0x84000000 | 0xbfe4f
1 | way 0 | set 10 | @ 0x6e280 | 0x84000000 | 0xbfe50 | 0x84000000 | 0xbfe51 | 0x84000000 | 0xbfe52 | 0x84000000 | 0xbfe53 | 0x84000000 | 0xbfe54 | 0x84000000 | 0xbfe55 | 0x84000000 | 0xbfe56 | 0x84000000 | 0xbfe57
1 | way 0 | set 11 | @ 0x962c0 | 0x84000000 | 0xbfe58 | 0x84000000 | 0xbfe59 | 0x84000000 | 0xbfe5a | 0x84000000 | 0xbfe5b | 0x84000000 | 0xbfe5c | 0x84000000 | 0xbfe5d | 0x84000000 | 0xbfe5e | 0x84000000 | 0xbfe5f
1 | way 0 | set 12 | @ 0x96300 | 0x84000000 | 0xbfe60 | 0x84000000 | 0xbfe61 | 0x84000000 | 0xbfe62 | 0x84000000 | 0xbfe63 | 0x84000000 | 0xbfe64 | 0x84000000 | 0xbfe65 | 0x84000000 | 0xbfe66 | 0x84000000 | 0xbfe67
1 | way 0 | set 13 | @ 0xbc340 | 0x84000000 | 0xbfe68 | 0x84000000 | 0xbfe69 | 0x84000000 | 0xbfe6a | 0x84000000 | 0xbfe6b | 0x84000000 | 0xbfe6c | 0x84000000 | 0xbfe6d | 0x84000000 | 0xbfe6e | 0x84000000 | 0xbfe6f
1 | way 0 | set 14 | @ 0x96380 | 0x84000000 | 0xbfe70 | 0x84000000 | 0xbfe71 | 0x84000000 | 0xbfe72 | 0x84000000 | 0xbfe73 | 0x84000000 | 0xbfe74 | 0x84000000 | 0xbfe75 | 0x84000000 | 0xbfe76 | 0x84000000 | 0xbfe77
1 | way 0 | set 15 | @ 0xbfc043c0 | 0xff0106d | 0 | 0x3c0e821 | 0x8fbf0014 | 0x8fbe0010 | 0x27bd0018 | 0x3e00008 | 0 | 0x33323130 | 0x37363534 | 0x42413938 | 0x46454443 | 0 | 0x33323130 | 0x37363534 | 0x3938
1 | way 0 | set 16 | @ 0xbfc0d400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x2fc | 0 | 0x800000 | 0xe000 | 0 | 0x65646f63 | 0
1 | way 0 | set 17 | @ 0xbfc04440 | 0x6974636e | 0x62206e6f | 0x5f746f6f | 0x67657370 | 0x7465675f | 0xa2928 | 0x6f666e55 | 0x20646e75 | 0x65676170 | 0x62617420 | 0x6620656c | 0x7620726f | 0x63617073 | 0x2065 | 0xa | 0x4f425b0a
1 | way 0 | set 18 | @ 0xbfc0d480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x240c | 0 | 0x400000 | 0xf000 | 0 | 0x62617470 | 0 | 0 | 0
1 | way 0 | set 19 | @ 0xbfc0c4c0 | 0x645f6c65 | 0x617461 | 0 | 0 | 0 | 0 | 0x80010000 | 0x8000 | 0x4000 | 0 | 0xa | 0 | 0x1 | 0x4 | 0x5f676573 | 0x6e72656b
1 | way 0 | set 20 | @ 0xbfc0d500 | 0 | 0 | 0 | 0 | 0x2 | 0x12000 | 0xd | 0x300000 | 0x12000 | 0 | 0x63617473 | 0x705f6b | 0 | 0 | 0 | 0
1 | way 0 | set 21 | @ 0xbfc0c540 | 0x695f6c65 | 0x74696e | 0 | 0 | 0 | 0 | 0x80090000 | 0xd000 | 0x1000 | 0 | 0xc | 0 | 0x1 | 0x6 | 0x5f676573 | 0x666266
1 | way 0 | set 22 | @ 0xbfc0d580 | 0 | 0 | 0x6 | 0x10000 | 0 | 0x10000 | 0x24000 | 0 | 0x63617473 | 0x635f6b | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 23 | @ 0xbfc0c5c0 | 0 | 0 | 0 | 0 | 0 | 0x20000000 | 0xf00000 | 0xf00000 | 0x1000 | 0x3 | 0x2 | 0x1 | 0x1 | 0x8 | 0x5f676573 | 0x636f69
1 | way 0 | set 24 | @ 0xbfc0c600 | 0 | 0 | 0 | 0 | 0 | 0 | 0xbff10000 | 0xbff10000 | 0x1000 | 0x4 | 0x2 | 0x1 | 0x1 | 0x9 | 0x5f676573 | 0x797474
1 | way 0 | set 25 | @ 0xbfc0c640 | 0 | 0 | 0 | 0 | 0 | 0 | 0xbff20000 | 0xbff20000 | 0x1000 | 0x5 | 0x2 | 0x1 | 0x1 | 0xa | 0x5f676573 | 0x616d64
1 | way 0 | set 26 | @ 0xbfc0c680 | 0 | 0 | 0 | 0 | 0 | 0 | 0xf30000 | 0xf30000 | 0x1000 | 0x6 | 0x2 | 0x1 | 0x1 | 0xb | 0x5f676573 | 0x646367
1 | way 0 | set 27 | @ 0xbfc0c6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xf50000 | 0xf50000 | 0x1000 | 0x8 | 0x2 | 0x1 | 0x1 | 0xc | 0x5f676573 | 0x626f69
1 | way 0 | set 28 | @ 0xbfc0c700 | 0 | 0 | 0 | 0 | 0 | 0 | 0xff0000 | 0xff0000 | 0x1000 | 0xa | 0x2 | 0x1 | 0x1 | 0xd | 0x5f676573 | 0x63696e
1 | way 0 | set 29 | @ 0xbfc0c740 | 0 | 0 | 0 | 0 | 0 | 0 | 0xbffa0000 | 0xbffa0000 | 0x1000 | 0x7 | 0x2 | 0x1 | 0x1 | 0xe | 0x5f676573 | 0x61746164
1 | way 0 | set 30 | @ 0xbc780 | 0x84000000 | 0xbfef0 | 0x84000000 | 0xbfef1 | 0x84000000 | 0xbfef2 | 0x84000000 | 0xbfef3 | 0x84000000 | 0xbfef4 | 0x84000000 | 0xbfef5 | 0x84000000 | 0xbfef6 | 0x84000000 | 0xbfef7
1 | way 0 | set 31 | @ 0x697c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xc000006f | 0xc000006e
1 | way 0 | set 32 | @ 0xb8800 | 0x88000000 | 0xb4 | 0x88000000 | 0xb5 | 0x88000000 | 0xb6 | 0x88000000 | 0xb7 | 0x88000000 | 0xb8 | 0x88000000 | 0xb9 | 0x88000000 | 0xba | 0x88000000 | 0xbb
1 | way 0 | set 33 | @ 0xbfc0d840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x94 | 0 | 0x800000 | 0x65000 | 0 | 0x65646f63 | 0 | 0 | 0
1 | way 0 | set 34 | @ 0xb8880 | 0x88000000 | 0xc4 | 0x88000000 | 0xc5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 35 | @ 0x948c0 | 0x84000000 | 0xbfd18 | 0x84000000 | 0xbfd19 | 0x84000000 | 0xbfd1a | 0x84000000 | 0xbfd1b | 0x84000000 | 0xbfd1c | 0x84000000 | 0xbfd1d | 0x84000000 | 0xbfd1e | 0x84000000 | 0xbfd1f
1 | way 0 | set 36 | @ 0xba900 | 0x84000000 | 0xbfd20 | 0x84000000 | 0xbfd21 | 0x84000000 | 0xbfd22 | 0x84000000 | 0xbfd23 | 0x84000000 | 0xbfd24 | 0x84000000 | 0xbfd25 | 0x84000000 | 0xbfd26 | 0x84000000 | 0xbfd27
1 | way 0 | set 37 | @ 0xbfc0d940 | 0 | 0 | 0x2 | 0x12000 | 0xd | 0x300000 | 0x68000 | 0 | 0x63617473 | 0x6b | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 38 | @ 0xba980 | 0x84000000 | 0xbfd30 | 0x84000000 | 0xbfd31 | 0x84000000 | 0xbfd32 | 0x84000000 | 0xbfd33 | 0x84000000 | 0xbfd34 | 0x84000000 | 0xbfd35 | 0x84000000 | 0xbfd36 | 0x84000000 | 0xbfd37
1 | way 0 | set 39 | @ 0x949c0 | 0x84000000 | 0xbfd38 | 0x84000000 | 0xbfd39 | 0x84000000 | 0xbfd3a | 0x84000000 | 0xbfd3b | 0x84000000 | 0xbfd3c | 0x84000000 | 0xbfd3d | 0x84000000 | 0xbfd3e | 0x84000000 | 0xbfd3f
1 | way 0 | set 40 | @ 0x94a00 | 0x84000000 | 0xbfd40 | 0x84000000 | 0xbfd41 | 0x84000000 | 0xbfd42 | 0x84000000 | 0xbfd43 | 0x84000000 | 0xbfd44 | 0x84000000 | 0xbfd45 | 0x84000000 | 0xbfd46 | 0x84000000 | 0xbfd47
1 | way 0 | set 41 | @ 0x94a40 | 0x84000000 | 0xbfd48 | 0x84000000 | 0xbfd49 | 0x84000000 | 0xbfd4a | 0x84000000 | 0xbfd4b | 0x84000000 | 0xbfd4c | 0x84000000 | 0xbfd4d | 0x84000000 | 0xbfd4e | 0x84000000 | 0xbfd4f
1 | way 0 | set 42 | @ 0xbda80 | 0x84000000 | 0xf50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 43 | @ 0xbaac0 | 0x84000000 | 0xbfd58 | 0x84000000 | 0xbfd59 | 0x84000000 | 0xbfd5a | 0x84000000 | 0xbfd5b | 0x84000000 | 0xbfd5c | 0x84000000 | 0xbfd5d | 0x84000000 | 0xbfd5e | 0x84000000 | 0xbfd5f
1 | way 0 | set 44 | @ 0xbab00 | 0x84000000 | 0xbfd60 | 0x84000000 | 0xbfd61 | 0x84000000 | 0xbfd62 | 0x84000000 | 0xbfd63 | 0x84000000 | 0xbfd64 | 0x84000000 | 0xbfd65 | 0x84000000 | 0xbfd66 | 0x84000000 | 0xbfd67
1 | way 0 | set 45 | @ 0xbfc04b40 | 0x7461636f | 0x2073726f | 0x74696e69 | 0x696c6169 | 0x69746173 | 0x63206e6f | 0x6c706d6f | 0x64657465 | 0x20746120 | 0x6c637963 | 0x2065 | 0x4f425b0a | 0x205d544f | 0x65676150 | 0x62615420 | 0x2073656c
1 | way 0 | set 46 | @ 0xbfc04b80 | 0x74696e69 | 0x696c6169 | 0x69746173 | 0x63206e6f | 0x6c706d6f | 0x64657465 | 0x20746120 | 0x6c637963 | 0x2065 | 0x4f425b0a | 0x205d544f | 0x6a626f56 | 0x6e692073 | 0x61697469 | 0x6173696c | 0x6e6f6974
1 | way 0 | set 47 | @ 0xbfc0cbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x800000 | 0xb0000 | 0x1000 | 0 | 0xb | 0 | 0x1 | 0x21 | 0x5f676573 | 0x65646f63
1 | way 0 | set 48 | @ 0xbfc0dc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0x6 | 0x10000 | 0 | 0x10000 | 0xa0000 | 0 | 0x61746164 | 0 | 0 | 0
1 | way 0 | set 49 | @ 0xbfc0cc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0x300000 | 0xb4000 | 0x12000 | 0 | 0x8 | 0 | 0x1 | 0x23 | 0x5f676573 | 0x63617473
1 | way 0 | set 50 | @ 0xbac80 | 0x84000000 | 0xbfd90 | 0x84000000 | 0xbfd91 | 0x84000000 | 0xbfd92 | 0x84000000 | 0xbfd93 | 0x84000000 | 0xbfd94 | 0x84000000 | 0xbfd95 | 0x84000000 | 0xbfd96 | 0x84000000 | 0xbfd97
1 | way 0 | set 51 | @ 0x18cc0 | 0x84000000 | 0xbfd98 | 0x84000000 | 0xbfd99 | 0x84000000 | 0xbfd9a | 0x84000000 | 0xbfd9b | 0x84000000 | 0xbfd9c | 0x84000000 | 0xbfd9d | 0x84000000 | 0xbfd9e | 0x84000000 | 0xbfd9f
1 | way 0 | set 52 | @ 0xbfc0dd00 | 0 | 0 | 0 | 0x1714 | 0 | 0x400000 | 0xb1000 | 0 | 0x62617470 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 53 | @ 0xbfc04d40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x10 | 0x10 | 0x10
1 | way 0 | set 54 | @ 0xbfc0dd80 | 0x2 | 0x12000 | 0xd | 0x300000 | 0xb4000 | 0 | 0x63617473 | 0x6b | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 55 | @ 0xbadc0 | 0x84000000 | 0xbfdb8 | 0x84000000 | 0xbfdb9 | 0x84000000 | 0xbfdba | 0x84000000 | 0xbfdbb | 0x84000000 | 0xbfdbc | 0x84000000 | 0xbfdbd | 0x84000000 | 0xbfdbe | 0x84000000 | 0xbfdbf
1 | way 0 | set 56 | @ 0x94e00 | 0x84000000 | 0xbfdc0 | 0x84000000 | 0xbfdc1 | 0x84000000 | 0xbfdc2 | 0x84000000 | 0xbfdc3 | 0x84000000 | 0xbfdc4 | 0x84000000 | 0xbfdc5 | 0x84000000 | 0xbfdc6 | 0x84000000 | 0xbfdc7
1 | way 0 | set 57 | @ 0xbfc04e40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x300000 | 0x300000 | 0x300000
1 | way 0 | set 58 | @ 0xbae80 | 0x84000000 | 0xbfdd0 | 0x84000000 | 0xbfdd1 | 0x84000000 | 0xbfdd2 | 0x84000000 | 0xbfdd3 | 0x84000000 | 0xbfdd4 | 0x84000000 | 0xbfdd5 | 0x84000000 | 0xbfdd6 | 0x84000000 | 0xbfdd7
1 | way 0 | set 59 | @ 0xbaec0 | 0x84000000 | 0xbfdd8 | 0x84000000 | 0xbfdd9 | 0x84000000 | 0xbfdda | 0x84000000 | 0xbfddb | 0x84000000 | 0xbfddc | 0x84000000 | 0xbfddd | 0x84000000 | 0xbfdde | 0x84000000 | 0xbfddf
1 | way 0 | set 60 | @ 0x3f00 | 0x2 | 0 | 0 | 0 | 0 | 0x101 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 61 | @ 0xbfc0af40 | 0x400000 | 0x800000 | 0xbfc0dc30 | 0 | 0xffffffff | 0xffffffff | 0x7 | 0x300000 | 0 | 0x5a | 0xff13 | 0xbfc0067c | 0x101 | 0 | 0x1 | 0x3
1 | way 0 | set 62 | @ 0xbfc0af80 | 0x1 | 0x20 | 0x4 | 0 | 0x1 | 0x7 | 0x4 | 0 | 0x7 | 0xbff20000 | 0x1 | 0xbfc0afb0 | 0xbfc0afcb | 0xbfc0e00c | 0xbfc0dfec | 0xbfc0ccb8
1 | way 0 | set 63 | @ 0xbfc0afc0 | 0x3 | 0x7 | 0x31c0c08c | 0x35373936 | 0xbf003136 | 0x1 | 0xbfc0c000 | 0xbff20000 | 0xbfc0afe8 | 0xbfc0afe8 | 0xbfc04478 | 0 | 0 | 0 | 0 | 0xbfc00524
1 | way 1 | set 0 | @ 0x18000 | 0xae000000 | 0xbfc00 | 0x8e000000 | 0xbfc01 | 0x8e000000 | 0xbfc02 | 0xae000000 | 0xbfc03 | 0xae400000 | 0xbfc04 | 0x8e000000 | 0xbfc05 | 0 | 0 | 0 | 0
1 | way 1 | set 1 | @ 0xba040 | 0x8c000000 | 0xbfc08 | 0x8c000000 | 0xbfc09 | 0xac400000 | 0xbfc0a | 0x8c000000 | 0xbfc0b | 0xac400000 | 0xbfc0c | 0xac000000 | 0xbfc0d | 0x8c000000 | 0xbfc0e | 0 | 0
1 | way 1 | set 2 | @ 0xbfc0e080 | 0xe | 0x3 | 0x6 | 0 | 0xf | 0x3 | 0x7 | 0 | 0x10 | 0x2 | 0 | 0 | 0x11 | 0x2 | 0x1 | 0
1 | way 1 | set 3 | @ 0xb90c0 | 0x8d000000 | 0xce | 0x8d000000 | 0xcf | 0x8d000000 | 0xd0 | 0x8d000000 | 0xd1 | 0x8d000000 | 0xd2 | 0x8d000000 | 0xd3 | 0x8d000000 | 0xd4 | 0x8d000000 | 0xd5
1 | way 1 | set 4 | @ 0xbc100 | 0x84000000 | 0xbfe20 | 0x84000000 | 0xbfe21 | 0x84000000 | 0xbfe22 | 0x84000000 | 0xbfe23 | 0x84000000 | 0xbfe24 | 0x84000000 | 0xbfe25 | 0x84000000 | 0xbfe26 | 0x84000000 | 0xbfe27
1 | way 1 | set 5 | @ 0xbfc0e140 | 0x1a | 0x2 | 0xa | 0 | 0x1b | 0x2 | 0xb | 0 | 0x1c | 0x2 | 0xc | 0 | 0x1d | 0x2 | 0xd | 0
1 | way 1 | set 6 | @ 0xbc180 | 0x84000000 | 0xbfe30 | 0x84000000 | 0xbfe31 | 0x84000000 | 0xbfe32 | 0x84000000 | 0xbfe33 | 0x84000000 | 0xbfe34 | 0x84000000 | 0xbfe35 | 0x84000000 | 0xbfe36 | 0x84000000 | 0xbfe37
1 | way 1 | set 7 | @ 0xbfc0e1c0 | 0x3 | 0x1 | 0 | 0x4 | 0x4 | 0x1 | 0x7 | 0x7 | 0x8 | 0x5 | 0x5 | 0x8 | 0x3 | 0x6 | 0x1 | 0x2
1 | way 1 | set 8 | @ 0xbfc0e200 | 0x3 | 0x5 | 0x6 | 0x2 | 0x1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 9 | @ 0x96240 | 0x84000000 | 0xbfe48 | 0x84000000 | 0xbfe49 | 0x84000000 | 0xbfe4a | 0x84000000 | 0xbfe4b | 0x84000000 | 0xbfe4c | 0x84000000 | 0xbfe4d | 0x84000000 | 0xbfe4e | 0x84000000 | 0xbfe4f
1 | way 1 | set 10 | @ 0x96280 | 0x84000000 | 0xbfe50 | 0x84000000 | 0xbfe51 | 0x84000000 | 0xbfe52 | 0x84000000 | 0xbfe53 | 0x84000000 | 0xbfe54 | 0x84000000 | 0xbfe55 | 0x84000000 | 0xbfe56 | 0x84000000 | 0xbfe57
1 | way 1 | set 11 | @ 0xbc2c0 | 0x84000000 | 0xbfe58 | 0x84000000 | 0xbfe59 | 0x84000000 | 0xbfe5a | 0x84000000 | 0xbfe5b | 0x84000000 | 0xbfe5c | 0x84000000 | 0xbfe5d | 0x84000000 | 0xbfe5e | 0x84000000 | 0xbfe5f
1 | way 1 | set 12 | @ 0xbc300 | 0x84000000 | 0xbfe60 | 0x84000000 | 0xbfe61 | 0x84000000 | 0xbfe62 | 0x84000000 | 0xbfe63 | 0x84000000 | 0xbfe64 | 0x84000000 | 0xbfe65 | 0x84000000 | 0xbfe66 | 0x84000000 | 0xbfe67
1 | way 1 | set 13 | @ 0xbfc0c340 | 0x64636770 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x4 | 0x4 | 0x1 | 0x1c | 0x1d | 0x5 | 0x70736964
1 | way 1 | set 14 | @ 0xbfc0c380 | 0x79616c | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x4 | 0x4 | 0x1 | 0x20 | 0x21 | 0x6 | 0x5f676573 | 0x746f6f62
1 | way 1 | set 15 | @ 0xbfc0c3c0 | 0x646f635f | 0x65 | 0 | 0 | 0 | 0 | 0xbfc00000 | 0xbfc00000 | 0x6000 | 0x1 | 0xe | 0x1 | 0x1 | 0 | 0x5f676573 | 0x746f6f62
1 | way 1 | set 16 | @ 0xbb400 | 0x84000000 | 0xc | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 17 | @ 0xbfc0c440 | 0x70616d5f | 0x676e6970 | 0 | 0 | 0 | 0 | 0xbfc0c000 | 0xbfc0c000 | 0x3000 | 0x1 | 0xa | 0x1 | 0x1 | 0x2 | 0x5f676573 | 0x6e72656b
1 | way 1 | set 18 | @ 0x19480 | 0x8a000000 | 0xd | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 19 | @ 0xbc4c0 | 0x84000000 | 0xbfe98 | 0x84000000 | 0xbfe99 | 0x84000000 | 0xbfe9a | 0x84000000 | 0xbfe9b | 0x84000000 | 0xbfe9c | 0x84000000 | 0xbfe9d | 0x84000000 | 0xbfe9e | 0x84000000 | 0xbfe9f
1 | way 1 | set 20 | @ 0x96500 | 0x84000000 | 0xbfea0 | 0x84000000 | 0xbfea1 | 0x84000000 | 0xbfea2 | 0x84000000 | 0xbfea3 | 0x84000000 | 0xbfea4 | 0x84000000 | 0xbfea5 | 0x84000000 | 0xbfea6 | 0x84000000 | 0xbfea7
1 | way 1 | set 21 | @ 0xbc540 | 0x84000000 | 0xbfea8 | 0x84000000 | 0xbfea9 | 0x84000000 | 0xbfeaa | 0x84000000 | 0xbfeab | 0x84000000 | 0xbfeac | 0x84000000 | 0xbfead | 0x84000000 | 0xbfeae | 0x84000000 | 0xbfeaf
1 | way 1 | set 22 | @ 0x96580 | 0x84000000 | 0xbfeb0 | 0x84000000 | 0xbfeb1 | 0x84000000 | 0xbfeb2 | 0x84000000 | 0xbfeb3 | 0x84000000 | 0xbfeb4 | 0x84000000 | 0xbfeb5 | 0x84000000 | 0xbfeb6 | 0x84000000 | 0xbfeb7
1 | way 1 | set 23 | @ 0xbc5c0 | 0x84000000 | 0xbfeb8 | 0x84000000 | 0xbfeb9 | 0x84000000 | 0xbfeba | 0x84000000 | 0xbfebb | 0x84000000 | 0xbfebc | 0x84000000 | 0xbfebd | 0x84000000 | 0xbfebe | 0x84000000 | 0xbfebf
1 | way 1 | set 24 | @ 0xbfc0d600 | 0x6 | 0x10000 | 0 | 0x20000 | 0x34000 | 0 | 0x63617473 | 0x41725f6b | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 25 | @ 0xbfc0d640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x6 | 0x10000
1 | way 1 | set 26 | @ 0xbfc0d680 | 0 | 0x30000 | 0x44000 | 0 | 0x63617473 | 0x42725f6b | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 27 | @ 0xbfc0d6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x6 | 0x10000 | 0 | 0x40000
1 | way 1 | set 28 | @ 0xbc700 | 0x84000000 | 0xbfee0 | 0x84000000 | 0xbfee1 | 0x84000000 | 0xbfee2 | 0x84000000 | 0xbfee3 | 0x84000000 | 0xbfee4 | 0x84000000 | 0xbfee5 | 0x84000000 | 0xbfee6 | 0x84000000 | 0xbfee7
1 | way 1 | set 29 | @ 0xbfc0d740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x4 | 0x20 | 0 | 0x50000 | 0x64000 | 0x1
1 | way 1 | set 30 | @ 0x1a780 | 0x84000000 | 0xbfef0 | 0x84000000 | 0xbfef1 | 0x84000000 | 0xbfef2 | 0x84000000 | 0xbfef3 | 0x84000000 | 0xbfef4 | 0x84000000 | 0xbfef5 | 0x84000000 | 0xbfef6 | 0x84000000 | 0xbfef7
1 | way 1 | set 31 | @ 0x8f7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xc0000094 | 0xc0000096
1 | way 1 | set 32 | @ 0xba800 | 0x84000000 | 0xbfd00 | 0x84000000 | 0xbfd01 | 0x84000000 | 0xbfd02 | 0x84000000 | 0xbfd03 | 0x84000000 | 0xbfd04 | 0x84000000 | 0xbfd05 | 0x84000000 | 0xbfd06 | 0x84000000 | 0xbfd07
1 | way 1 | set 33 | @ 0xb8840 | 0x88000000 | 0xbc | 0x88000000 | 0xbd | 0x88000000 | 0xbe | 0x88000000 | 0xbf | 0x88000000 | 0xc0 | 0x88000000 | 0xc1 | 0x88000000 | 0xc2 | 0x88000000 | 0xc3
1 | way 1 | set 34 | @ 0xba880 | 0x84000000 | 0xbfd10 | 0x84000000 | 0xbfd11 | 0x84000000 | 0xbfd12 | 0x84000000 | 0xbfd13 | 0x84000000 | 0xbfd14 | 0x84000000 | 0xbfd15 | 0x84000000 | 0xbfd16 | 0x84000000 | 0xbfd17
1 | way 1 | set 35 | @ 0xba8c0 | 0x84000000 | 0xbfd18 | 0x84000000 | 0xbfd19 | 0x84000000 | 0xbfd1a | 0x84000000 | 0xbfd1b | 0x84000000 | 0xbfd1c | 0x84000000 | 0xbfd1d | 0x84000000 | 0xbfd1e | 0x84000000 | 0xbfd1f
1 | way 1 | set 36 | @ 0xbc900 | 0xa4400000 | 0xbff20 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 37 | @ 0xba940 | 0x84000000 | 0xbfd28 | 0x84000000 | 0xbfd29 | 0x84000000 | 0xbfd2a | 0x84000000 | 0xbfd2b | 0x84000000 | 0xbfd2c | 0x84000000 | 0xbfd2d | 0x84000000 | 0xbfd2e | 0x84000000 | 0xbfd2f
1 | way 1 | set 38 | @ 0xbd980 | 0x84000000 | 0xf30 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 39 | @ 0xba9c0 | 0x84000000 | 0xbfd38 | 0x84000000 | 0xbfd39 | 0x84000000 | 0xbfd3a | 0x84000000 | 0xbfd3b | 0x84000000 | 0xbfd3c | 0x84000000 | 0xbfd3d | 0x84000000 | 0xbfd3e | 0x84000000 | 0xbfd3f
1 | way 1 | set 40 | @ 0xbaa00 | 0x84000000 | 0xbfd40 | 0x84000000 | 0xbfd41 | 0x84000000 | 0xbfd42 | 0x84000000 | 0xbfd43 | 0x84000000 | 0xbfd44 | 0x84000000 | 0xbfd45 | 0x84000000 | 0xbfd46 | 0x84000000 | 0xbfd47
1 | way 1 | set 41 | @ 0xbaa40 | 0x84000000 | 0xbfd48 | 0x84000000 | 0xbfd49 | 0x84000000 | 0xbfd4a | 0x84000000 | 0xbfd4b | 0x84000000 | 0xbfd4c | 0x84000000 | 0xbfd4d | 0x84000000 | 0xbfd4e | 0x84000000 | 0xbfd4f
1 | way 1 | set 42 | @ 0xbfc0da80 | 0x666c65 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xf8 | 0 | 0x800000
1 | way 1 | set 43 | @ 0x18ac0 | 0x84000000 | 0xbfd58 | 0x84000000 | 0xbfd59 | 0x84000000 | 0xbfd5a | 0x84000000 | 0xbfd5b | 0x84000000 | 0xbfd5c | 0x84000000 | 0xbfd5d | 0x84000000 | 0xbfd5e | 0x84000000 | 0xbfd5f
1 | way 1 | set 44 | @ 0xbfc0db00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x1620 | 0 | 0x400000 | 0x8b000 | 0
1 | way 1 | set 45 | @ 0xbfc0cb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0x300000 | 0x8e000 | 0x12000 | 0 | 0x8 | 0 | 0x1 | 0x1f | 0x5f676573 | 0x63617473
1 | way 1 | set 46 | @ 0xbfc0db80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x2 | 0x12000 | 0xd | 0x300000 | 0x8e000 | 0 | 0x63617473 | 0x6b
1 | way 1 | set 47 | @ 0xbabc0 | 0x84000000 | 0xbfd78 | 0x84000000 | 0xbfd79 | 0x84000000 | 0xbfd7a | 0x84000000 | 0xbfd7b | 0x84000000 | 0xbfd7c | 0x84000000 | 0xbfd7d | 0x84000000 | 0xbfd7e | 0x84000000 | 0xbfd7f
1 | way 1 | set 48 | @ 0xbfc04c00 | 0x64657465 | 0x20746120 | 0x6c637963 | 0x2065 | 0x4f425b0a | 0x205d544f | 0x20554d4d | 0x69746361 | 0x69746176 | 0x63206e6f | 0x6c706d6f | 0x64657465 | 0x20746120 | 0x6c637963 | 0x2065 | 0x4f425b0a
1 | way 1 | set 49 | @ 0xbfc04c40 | 0x205d544f | 0x65686353 | 0x656c7564 | 0x69207372 | 0x6974696e | 0x73696c61 | 0x6f697461 | 0x6f63206e | 0x656c706d | 0x20646574 | 0x63207461 | 0x656c6379 | 0x20 | 0x8 | 0x8 | 0x8
1 | way 1 | set 50 | @ 0xbfc04c80 | 0x8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 51 | @ 0x6fcc0 | 0x84000000 | 0xbfd98 | 0x84000000 | 0xbfd99 | 0x84000000 | 0xbfd9a | 0x84000000 | 0xbfd9b | 0x84000000 | 0xbfd9c | 0x84000000 | 0xbfd9d | 0x84000000 | 0xbfd9e | 0x84000000 | 0xbfd9f
1 | way 1 | set 52 | @ 0xbad00 | 0x84000000 | 0xbfda0 | 0x84000000 | 0xbfda1 | 0x84000000 | 0xbfda2 | 0x84000000 | 0xbfda3 | 0x84000000 | 0xbfda4 | 0x84000000 | 0xbfda5 | 0x84000000 | 0xbfda6 | 0x84000000 | 0xbfda7
1 | way 1 | set 53 | @ 0xbad40 | 0x84000000 | 0xbfda8 | 0x84000000 | 0xbfda9 | 0x84000000 | 0xbfdaa | 0x84000000 | 0xbfdab | 0x84000000 | 0xbfdac | 0x84000000 | 0xbfdad | 0x84000000 | 0xbfdae | 0x84000000 | 0xbfdaf
1 | way 1 | set 54 | @ 0xbfc04d80 | 0x10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 55 | @ 0xbfc0ddc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x6 | 0x10000
1 | way 1 | set 56 | @ 0xbae00 | 0x84000000 | 0xbfdc0 | 0x84000000 | 0xbfdc1 | 0x84000000 | 0xbfdc2 | 0x84000000 | 0xbfdc3 | 0x84000000 | 0xbfdc4 | 0x84000000 | 0xbfdc5 | 0x84000000 | 0xbfdc6 | 0x84000000 | 0xbfdc7
1 | way 1 | set 57 | @ 0xbfc0de40 | 0 | 0x1 | 0 | 0 | 0 | 0x736e6f63 | 0x72656d75 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x1 | 0x4
1 | way 1 | set 58 | @ 0xbfc0de80 | 0xffffffff | 0x1 | 0x1 | 0 | 0 | 0 | 0x74756f72 | 0x415f7265 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x2
1 | way 1 | set 59 | @ 0xbfc0aec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xf00 | 0
1 | way 1 | set 60 | @ 0xbfc0af00 | 0xbc | 0 | 0 | 0xbfc0af10 | 0 | 0 | 0x2f | 0x1 | 0 | 0 | 0 | 0 | 0 | 0 | 0x20000 | 0x24
1 | way 1 | set 61 | @ 0xbfc04f40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x1000 | 0x2000
1 | way 1 | set 62 | @ 0xbfc04f80 | 0x3000 | 0x12000 | 0x68000 | 0x8e000 | 0xb4000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 63 | @ 0xbfc0dfc0 | 0 | 0 | 0 | 0 | 0x3 | 0xffffffff | 0 | 0x1 | 0 | 0 | 0x1 | 0x19 | 0 | 0x1 | 0x19 | 0x1
1 | way 2 | set 0 | @ 0xba000 | 0xae000000 | 0xbfc00 | 0x8e000000 | 0xbfc01 | 0x8e000000 | 0xbfc02 | 0xae000000 | 0xbfc03 | 0xae000000 | 0xbfc04 | 0x8e000000 | 0xbfc05 | 0 | 0 | 0 | 0
1 | way 2 | set 1 | @ 0xbfc0e040 | 0xa | 0x3 | 0x2 | 0 | 0xb | 0x3 | 0x3 | 0 | 0xc | 0x3 | 0x4 | 0 | 0xd | 0x3 | 0x5 | 0
1 | way 2 | set 2 | @ 0xbc080 | 0x84000000 | 0xbfe10 | 0x84000000 | 0xbfe11 | 0x84000000 | 0xbfe12 | 0x84000000 | 0xbfe13 | 0x84000000 | 0xbfe14 | 0x84000000 | 0xbfe15 | 0x84000000 | 0xbfe16 | 0x84000000 | 0xbfe17
1 | way 2 | set 3 | @ 0x930c0 | 0x8d000000 | 0xa8 | 0x8d000000 | 0xa9 | 0x8d000000 | 0xaa | 0x8d000000 | 0xab | 0x8d000000 | 0xac | 0x8d000000 | 0xad | 0x8d000000 | 0xae | 0x8d000000 | 0xaf
1 | way 2 | set 4 | @ 0xbfc0c100 | 0 | 0 | 0 | 0 | 0 | 0xbfd00000 | 0x200000 | 0x2 | 0 | 0xbfd00000 | 0x47455350 | 0x5543495f | 0 | 0 | 0 | 0
1 | way 2 | set 5 | @ 0xbc140 | 0x84000000 | 0xbfe28 | 0x84000000 | 0xbfe29 | 0x84000000 | 0xbfe2a | 0x84000000 | 0xbfe2b | 0x84000000 | 0xbfe2c | 0x84000000 | 0xbfe2d | 0x84000000 | 0xbfe2e | 0x84000000 | 0xbfe2f
1 | way 2 | set 6 | @ 0xbfc0c180 | 0x1000 | 0x2 | 0 | 0xbff10000 | 0x47455350 | 0x5954545f | 0 | 0 | 0 | 0 | 0 | 0 | 0xbff20000 | 0x1000 | 0x2 | 0
1 | way 2 | set 7 | @ 0x961c0 | 0x84000000 | 0xbfe38 | 0x84000000 | 0xbfe39 | 0x84000000 | 0xbfe3a | 0x84000000 | 0xbfe3b | 0x84000000 | 0xbfe3c | 0x84000000 | 0xbfe3d | 0x84000000 | 0xbfe3e | 0x84000000 | 0xbfe3f
1 | way 2 | set 8 | @ 0xbc200 | 0x84000000 | 0xbfe40 | 0x84000000 | 0xbfe41 | 0x84000000 | 0xbfe42 | 0x84000000 | 0xbfe43 | 0x84000000 | 0xbfe44 | 0x84000000 | 0xbfe45 | 0x84000000 | 0xbfe46 | 0x84000000 | 0xbfe47
1 | way 2 | set 9 | @ 0xbc240 | 0x84000000 | 0xbfe48 | 0x84000000 | 0xbfe49 | 0x84000000 | 0xbfe4a | 0x84000000 | 0xbfe4b | 0x84000000 | 0xbfe4c | 0x84000000 | 0xbfe4d | 0x84000000 | 0xbfe4e | 0x84000000 | 0xbfe4f
1 | way 2 | set 10 | @ 0xbc280 | 0x84000000 | 0xbfe50 | 0x84000000 | 0xbfe51 | 0x84000000 | 0xbfe52 | 0x84000000 | 0xbfe53 | 0x84000000 | 0xbfe54 | 0x84000000 | 0xbfe55 | 0x84000000 | 0xbfe56 | 0x84000000 | 0xbfe57
1 | way 2 | set 11 | @ 0xbfc0c2c0 | 0 | 0xff0000 | 0x74756f72 | 0x7265 | 0 | 0 | 0 | 0 | 0 | 0x20000000 | 0 | 0x8 | 0x9 | 0x4 | 0xf | 0xf
1 | way 2 | set 12 | @ 0xbfc0c300 | 0 | 0x6c6c6568 | 0x6f | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x5 | 0x5 | 0x1 | 0x17 | 0x18 | 0x4
1 | way 2 | set 13 | @ 0x6e340 | 0x84000000 | 0xbfe68 | 0x84000000 | 0xbfe69 | 0x84000000 | 0xbfe6a | 0x84000000 | 0xbfe6b | 0x84000000 | 0xbfe6c | 0x84000000 | 0xbfe6d | 0x84000000 | 0xbfe6e | 0x84000000 | 0xbfe6f
1 | way 2 | set 14 | @ 0xbc380 | 0x84000000 | 0xbfe70 | 0x84000000 | 0xbfe71 | 0x84000000 | 0xbfe72 | 0x84000000 | 0xbfe73 | 0x84000000 | 0xbfe74 | 0x84000000 | 0xbfe75 | 0x84000000 | 0xbfe76 | 0x84000000 | 0xbfe77
1 | way 2 | set 15 | @ 0xbc3c0 | 0x84000000 | 0xbfe78 | 0x84000000 | 0xbfe79 | 0x84000000 | 0xbfe7a | 0x84000000 | 0xbfe7b | 0x84000000 | 0xbfe7c | 0x84000000 | 0xbfe7d | 0x84000000 | 0xbfe7e | 0x84000000 | 0xbfe7f
1 | way 2 | set 16 | @ 0xbc400 | 0x84000000 | 0xbfe80 | 0x84000000 | 0xbfe81 | 0x84000000 | 0xbfe82 | 0x84000000 | 0xbfe83 | 0x84000000 | 0xbfe84 | 0x84000000 | 0xbfe85 | 0x84000000 | 0xbfe86 | 0x84000000 | 0xbfe87
1 | way 2 | set 17 | @ 0xbc440 | 0x84000000 | 0xbfe88 | 0x84000000 | 0xbfe89 | 0x84000000 | 0xbfe8a | 0x84000000 | 0xbfe8b | 0x84000000 | 0xbfe8c | 0x84000000 | 0xbfe8d | 0x84000000 | 0xbfe8e | 0x84000000 | 0xbfe8f
1 | way 2 | set 18 | @ 0xbc480 | 0x84000000 | 0xbfe90 | 0x84000000 | 0xbfe91 | 0x84000000 | 0xbfe92 | 0x84000000 | 0xbfe93 | 0x84000000 | 0xbfe94 | 0x84000000 | 0xbfe95 | 0x84000000 | 0xbfe96 | 0x84000000 | 0xbfe97
1 | way 2 | set 19 | @ 0x6e4c0 | 0x84000000 | 0xbfe98 | 0x84000000 | 0xbfe99 | 0x84000000 | 0xbfe9a | 0x84000000 | 0xbfe9b | 0x84000000 | 0xbfe9c | 0x84000000 | 0xbfe9d | 0x84000000 | 0xbfe9e | 0x84000000 | 0xbfe9f
1 | way 2 | set 20 | @ 0xbc500 | 0x84000000 | 0xbfea0 | 0x84000000 | 0xbfea1 | 0x84000000 | 0xbfea2 | 0x84000000 | 0xbfea3 | 0x84000000 | 0xbfea4 | 0x84000000 | 0xbfea5 | 0x84000000 | 0xbfea6 | 0x84000000 | 0xbfea7
1 | way 2 | set 21 | @ 0x6e540 | 0x84000000 | 0xbfea8 | 0x84000000 | 0xbfea9 | 0x84000000 | 0xbfeaa | 0x84000000 | 0xbfeab | 0x84000000 | 0xbfeac | 0x84000000 | 0xbfead | 0x84000000 | 0xbfeae | 0x84000000 | 0xbfeaf
1 | way 2 | set 22 | @ 0xbc580 | 0x84000000 | 0xbfeb0 | 0x84000000 | 0xbfeb1 | 0x84000000 | 0xbfeb2 | 0x84000000 | 0xbfeb3 | 0x84000000 | 0xbfeb4 | 0x84000000 | 0xbfeb5 | 0x84000000 | 0xbfeb6 | 0x84000000 | 0xbfeb7
1 | way 2 | set 23 | @ 0x6e5c0 | 0x84000000 | 0xbfeb8 | 0x84000000 | 0xbfeb9 | 0x84000000 | 0xbfeba | 0x84000000 | 0xbfebb | 0x84000000 | 0xbfebc | 0x84000000 | 0xbfebd | 0x84000000 | 0xbfebe | 0x84000000 | 0xbfebf
1 | way 2 | set 24 | @ 0xbc600 | 0x84000000 | 0xbfec0 | 0x84000000 | 0xbfec1 | 0x84000000 | 0xbfec2 | 0x84000000 | 0xbfec3 | 0x84000000 | 0xbfec4 | 0x84000000 | 0xbfec5 | 0x84000000 | 0xbfec6 | 0x84000000 | 0xbfec7
1 | way 2 | set 25 | @ 0xbc640 | 0x84000000 | 0xbfec8 | 0x84000000 | 0xbfec9 | 0x84000000 | 0xbfeca | 0x84000000 | 0xbfecb | 0x84000000 | 0xbfecc | 0x84000000 | 0xbfecd | 0x84000000 | 0xbfece | 0x84000000 | 0xbfecf
1 | way 2 | set 26 | @ 0xbc680 | 0x84000000 | 0xbfed0 | 0x84000000 | 0xbfed1 | 0x84000000 | 0xbfed2 | 0x84000000 | 0xbfed3 | 0x84000000 | 0xbfed4 | 0x84000000 | 0xbfed5 | 0x84000000 | 0xbfed6 | 0x84000000 | 0xbfed7
1 | way 2 | set 27 | @ 0xbc6c0 | 0x84000000 | 0xbfed8 | 0x84000000 | 0xbfed9 | 0x84000000 | 0xbfeda | 0x84000000 | 0xbfedb | 0x84000000 | 0xbfedc | 0x84000000 | 0xbfedd | 0x84000000 | 0xbfede | 0x84000000 | 0xbfedf
1 | way 2 | set 28 | @ 0x6e700 | 0x84000000 | 0xbfee0 | 0x84000000 | 0xbfee1 | 0x84000000 | 0xbfee2 | 0x84000000 | 0xbfee3 | 0x84000000 | 0xbfee4 | 0x84000000 | 0xbfee5 | 0x84000000 | 0xbfee6 | 0x84000000 | 0xbfee7
1 | way 2 | set 29 | @ 0xbc740 | 0x84000000 | 0xbfee8 | 0x84000000 | 0xbfee9 | 0x84000000 | 0xbfeea | 0x84000000 | 0xbfeeb | 0x84000000 | 0xbfeec | 0x84000000 | 0xbfeed | 0x84000000 | 0xbfeee | 0x84000000 | 0xbfeef
1 | way 2 | set 30 | @ 0x6e780 | 0x84000000 | 0xbfef0 | 0x84000000 | 0xbfef1 | 0x84000000 | 0xbfef2 | 0x84000000 | 0xbfef3 | 0x84000000 | 0xbfef4 | 0x84000000 | 0xbfef5 | 0x84000000 | 0xbfef6 | 0x84000000 | 0xbfef7
1 | way 2 | set 31 | @ 0xb57c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xc00000ba | 0xc00000bc
1 | way 2 | set 32 | @ 0xbd800 | 0x84000000 | 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 33 | @ 0x92840 | 0x88000000 | 0x96 | 0x88000000 | 0x97 | 0x88000000 | 0x98 | 0x88000000 | 0x99 | 0x88000000 | 0x9a | 0x88000000 | 0x9b | 0x88000000 | 0x9c | 0x88000000 | 0x9d
1 | way 2 | set 34 | @ 0xbc880 | 0x84000000 | 0xbff10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 35 | @ 0xbfc0d8c0 | 0 | 0 | 0 | 0 | 0 | 0x1578 | 0 | 0x400000 | 0x66000 | 0 | 0x62617470 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 36 | @ 0x96900 | 0x84000000 | 0xbff20 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 37 | @ 0xbfc04940 | 0x4e495b0a | 0x45205449 | 0x524f5252 | 0x694d205d | 0x6e697373 | 0x54502067 | 0x66204241 | 0x7620726f | 0x63617073 | 0x2065 | 0xbfc02cf0 | 0xbfc02cf0 | 0xbfc02c44 | 0xbfc02ca0 | 0xbfc02a90 | 0xbfc02b98
1 | way 2 | set 38 | @ 0x97980 | 0x84000000 | 0xf30 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 39 | @ 0xbfc0d9c0 | 0x6 | 0x10000 | 0 | 0x10000 | 0x7a000 | 0 | 0x5f63696e | 0x32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 40 | @ 0xbfc0da00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x6 | 0x4000
1 | way 2 | set 41 | @ 0x18a40 | 0x84000000 | 0xbfd48 | 0x84000000 | 0xbfd49 | 0x84000000 | 0xbfd4a | 0x84000000 | 0xbfd4b | 0x84000000 | 0xbfd4c | 0x84000000 | 0xbfd4d | 0x84000000 | 0xbfd4e | 0x84000000 | 0xbfd4f
1 | way 2 | set 42 | @ 0x71a80 | 0x84000000 | 0xf50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 43 | @ 0x6fac0 | 0x84000000 | 0xbfd58 | 0x84000000 | 0xbfd59 | 0x84000000 | 0xbfd5a | 0x84000000 | 0xbfd5b | 0x84000000 | 0xbfd5c | 0x84000000 | 0xbfd5d | 0x84000000 | 0xbfd5e | 0x84000000 | 0xbfd5f
1 | way 2 | set 44 | @ 0x94b00 | 0x84000000 | 0xbfd60 | 0x84000000 | 0xbfd61 | 0x84000000 | 0xbfd62 | 0x84000000 | 0xbfd63 | 0x84000000 | 0xbfd64 | 0x84000000 | 0xbfd65 | 0x84000000 | 0xbfd66 | 0x84000000 | 0xbfd67
1 | way 2 | set 45 | @ 0xbab40 | 0x84000000 | 0xbfd68 | 0x84000000 | 0xbfd69 | 0x84000000 | 0xbfd6a | 0x84000000 | 0xbfd6b | 0x84000000 | 0xbfd6c | 0x84000000 | 0xbfd6d | 0x84000000 | 0xbfd6e | 0x84000000 | 0xbfd6f
1 | way 2 | set 46 | @ 0xbab80 | 0x84000000 | 0xbfd70 | 0x84000000 | 0xbfd71 | 0x84000000 | 0xbfd72 | 0x84000000 | 0xbfd73 | 0x84000000 | 0xbfd74 | 0x84000000 | 0xbfd75 | 0x84000000 | 0xbfd76 | 0x84000000 | 0xbfd77
1 | way 2 | set 47 | @ 0xbfc04bc0 | 0x6d6f6320 | 0x74656c70 | 0x61206465 | 0x79632074 | 0x20656c63 | 0x203a | 0x4f425b0a | 0x205d544f | 0x69726550 | 0x72656870 | 0x20736c61 | 0x74696e69 | 0x696c6169 | 0x69746173 | 0x63206e6f | 0x6c706d6f
1 | way 2 | set 48 | @ 0xbac00 | 0x84000000 | 0xbfd80 | 0x84000000 | 0xbfd81 | 0x84000000 | 0xbfd82 | 0x84000000 | 0xbfd83 | 0x84000000 | 0xbfd84 | 0x84000000 | 0xbfd85 | 0x84000000 | 0xbfd86 | 0x84000000 | 0xbfd87
1 | way 2 | set 49 | @ 0x94c40 | 0x84000000 | 0xbfd88 | 0x84000000 | 0xbfd89 | 0x84000000 | 0xbfd8a | 0x84000000 | 0xbfd8b | 0x84000000 | 0xbfd8c | 0x84000000 | 0xbfd8d | 0x84000000 | 0xbfd8e | 0x84000000 | 0xbfd8f
1 | way 2 | set 50 | @ 0xbfc0cc80 | 0x6b | 0 | 0 | 0 | 0 | 0 | 0x10000 | 0xc6000 | 0x10000 | 0 | 0xb | 0 | 0x1 | 0x24 | 0x746f6f62 | 0x646f635f
1 | way 2 | set 51 | @ 0x94cc0 | 0x84000000 | 0xbfd98 | 0x84000000 | 0xbfd99 | 0x84000000 | 0xbfd9a | 0x84000000 | 0xbfd9b | 0x84000000 | 0xbfd9c | 0x84000000 | 0xbfd9d | 0x84000000 | 0xbfd9e | 0x84000000 | 0xbfd9f
1 | way 2 | set 52 | @ 0x94d00 | 0x84000000 | 0xbfda0 | 0x84000000 | 0xbfda1 | 0x84000000 | 0xbfda2 | 0x84000000 | 0xbfda3 | 0x84000000 | 0xbfda4 | 0x84000000 | 0xbfda5 | 0x84000000 | 0xbfda6 | 0x84000000 | 0xbfda7
1 | way 2 | set 53 | @ 0x6fd40 | 0x84000000 | 0xbfda8 | 0x84000000 | 0xbfda9 | 0x84000000 | 0xbfdaa | 0x84000000 | 0xbfdab | 0x84000000 | 0xbfdac | 0x84000000 | 0xbfdad | 0x84000000 | 0xbfdae | 0x84000000 | 0xbfdaf
1 | way 2 | set 54 | @ 0xbad80 | 0x84000000 | 0xbfdb0 | 0x84000000 | 0xbfdb1 | 0x84000000 | 0xbfdb2 | 0x84000000 | 0xbfdb3 | 0x84000000 | 0xbfdb4 | 0x84000000 | 0xbfdb5 | 0x84000000 | 0xbfdb6 | 0x84000000 | 0xbfdb7
1 | way 2 | set 55 | @ 0x6fdc0 | 0x84000000 | 0xbfdb8 | 0x84000000 | 0xbfdb9 | 0x84000000 | 0xbfdba | 0x84000000 | 0xbfdbb | 0x84000000 | 0xbfdbc | 0x84000000 | 0xbfdbd | 0x84000000 | 0xbfdbe | 0x84000000 | 0xbfdbf
1 | way 2 | set 56 | @ 0xbfc0de00 | 0 | 0x10000 | 0xc6000 | 0 | 0x646f7270 | 0x72656375 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x1 | 0x3 | 0xffffffff
1 | way 2 | set 57 | @ 0x94e40 | 0x84000000 | 0xbfdc8 | 0x84000000 | 0xbfdc9 | 0x84000000 | 0xbfdca | 0x84000000 | 0xbfdcb | 0x84000000 | 0xbfdcc | 0x84000000 | 0xbfdcd | 0x84000000 | 0xbfdce | 0x84000000 | 0xbfdcf
1 | way 2 | set 58 | @ 0xbfc04e80 | 0x300000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 59 | @ 0xbfc0dec0 | 0x5 | 0xffffffff | 0x2 | 0x1 | 0 | 0 | 0 | 0x74756f72 | 0x425f7265 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 60 | @ 0x2f00 | 0x2 | 0 | 0 | 0 | 0x101 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 61 | @ 0xbaf40 | 0x84000000 | 0xbfde8 | 0x84000000 | 0xbfde9 | 0x84000000 | 0xbfdea | 0x84000000 | 0xbfdeb | 0x84000000 | 0xbfdec | 0x84000000 | 0xbfded | 0x84000000 | 0xbfdee | 0x84000000 | 0xbfdef
1 | way 2 | set 62 | @ 0xbfc0df80 | 0 | 0 | 0x3 | 0x3 | 0xffffffff | 0 | 0x1 | 0 | 0 | 0 | 0x6e69616d | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 63 | @ 0xbafc0 | 0x84000000 | 0xbfdf8 | 0x84000000 | 0xbfdf9 | 0x84000000 | 0xbfdfa | 0x84000000 | 0xbfdfb | 0x84000000 | 0xbfdfc | 0x84000000 | 0xbfdfd | 0x84000000 | 0xbfdfe | 0x84000000 | 0xbfdff
1 | way 3 | set 0 | @ 0xb0000 | 0x400000 | 0x2a2a200a | 0x6d69202a | 0x20656761 | 0x2a206425 | 0x61202a2a | 0x61642074 | 0x3d206574 | 0x20642520 | 0xa | 0x65686365 | 0x69672063 | 0x695f7465 | 0x725f636f | 0x20646165 | 0x61206425
1 | way 3 | set 1 | @ 0x6f040 | 0x8c000000 | 0xbfc08 | 0x8c000000 | 0xbfc09 | 0xac400000 | 0xbfc0a | 0x8c000000 | 0xbfc0b | 0xac000000 | 0xbfc0c | 0xac000000 | 0xbfc0d | 0x8c000000 | 0xbfc0e | 0 | 0
1 | way 3 | set 2 | @ 0x96080 | 0x84000000 | 0xbfe10 | 0x84000000 | 0xbfe11 | 0x84000000 | 0xbfe12 | 0x84000000 | 0xbfe13 | 0x84000000 | 0xbfe14 | 0x84000000 | 0xbfe15 | 0x84000000 | 0xbfe16 | 0x84000000 | 0xbfe17
1 | way 3 | set 3 | @ 0xbc0c0 | 0x84000000 | 0xbfe18 | 0x84000000 | 0xbfe19 | 0x84000000 | 0xbfe1a | 0x84000000 | 0xbfe1b | 0x84000000 | 0xbfe1c | 0x84000000 | 0xbfe1d | 0x84000000 | 0xbfe1e | 0x84000000 | 0xbfe1f
1 | way 3 | set 4 | @ 0x6e100 | 0x84000000 | 0xbfe20 | 0x84000000 | 0xbfe21 | 0x84000000 | 0xbfe22 | 0x84000000 | 0xbfe23 | 0x84000000 | 0xbfe24 | 0x84000000 | 0xbfe25 | 0x84000000 | 0xbfe26 | 0x84000000 | 0xbfe27
1 | way 3 | set 5 | @ 0x1a140 | 0x84000000 | 0xbfe28 | 0x84000000 | 0xbfe29 | 0x84000000 | 0xbfe2a | 0x84000000 | 0xbfe2b | 0x84000000 | 0xbfe2c | 0x84000000 | 0xbfe2d | 0x84000000 | 0xbfe2e | 0x84000000 | 0xbfe2f
1 | way 3 | set 6 | @ 0x6e180 | 0x84000000 | 0xbfe30 | 0x84000000 | 0xbfe31 | 0x84000000 | 0xbfe32 | 0x84000000 | 0xbfe33 | 0x84000000 | 0xbfe34 | 0x84000000 | 0xbfe35 | 0x84000000 | 0xbfe36 | 0x84000000 | 0xbfe37
1 | way 3 | set 7 | @ 0xbfc0c1c0 | 0xbff20000 | 0x47455350 | 0x414d445f | 0 | 0 | 0 | 0 | 0 | 0 | 0xf30000 | 0x1000 | 0x2 | 0 | 0xf30000 | 0x47455350 | 0x43494e5f
1 | way 3 | set 8 | @ 0x1a200 | 0x84000000 | 0xbfe40 | 0x84000000 | 0xbfe41 | 0x84000000 | 0xbfe42 | 0x84000000 | 0xbfe43 | 0x84000000 | 0xbfe44 | 0x84000000 | 0xbfe45 | 0x84000000 | 0xbfe46 | 0x84000000 | 0xbfe47
1 | way 3 | set 9 | @ 0x1a240 | 0x84000000 | 0xbfe48 | 0x84000000 | 0xbfe49 | 0x84000000 | 0xbfe4a | 0x84000000 | 0xbfe4b | 0x84000000 | 0xbfe4c | 0x84000000 | 0xbfe4d | 0x84000000 | 0xbfe4e | 0x84000000 | 0xbfe4f
1 | way 3 | set 10 | @ 0x1a280 | 0x84000000 | 0xbfe50 | 0x84000000 | 0xbfe51 | 0x84000000 | 0xbfe52 | 0x84000000 | 0xbfe53 | 0x84000000 | 0xbfe54 | 0x84000000 | 0xbfe55 | 0x84000000 | 0xbfe56 | 0x84000000 | 0xbfe57
1 | way 3 | set 11 | @ 0x6e2c0 | 0x84000000 | 0xbfe58 | 0x84000000 | 0xbfe59 | 0x84000000 | 0xbfe5a | 0x84000000 | 0xbfe5b | 0x84000000 | 0xbfe5c | 0x84000000 | 0xbfe5d | 0x84000000 | 0xbfe5e | 0x84000000 | 0xbfe5f
1 | way 3 | set 12 | @ 0x6e300 | 0x84000000 | 0xbfe60 | 0x84000000 | 0xbfe61 | 0x84000000 | 0xbfe62 | 0x84000000 | 0xbfe63 | 0x84000000 | 0xbfe64 | 0x84000000 | 0xbfe65 | 0x84000000 | 0xbfe66 | 0x84000000 | 0xbfe67
1 | way 3 | set 13 | @ 0x96340 | 0x84000000 | 0xbfe68 | 0x84000000 | 0xbfe69 | 0x84000000 | 0xbfe6a | 0x84000000 | 0xbfe6b | 0x84000000 | 0xbfe6c | 0x84000000 | 0xbfe6d | 0x84000000 | 0xbfe6e | 0x84000000 | 0xbfe6f
1 | way 3 | set 14 | @ 0x6e380 | 0x84000000 | 0xbfe70 | 0x84000000 | 0xbfe71 | 0x84000000 | 0xbfe72 | 0x84000000 | 0xbfe73 | 0x84000000 | 0xbfe74 | 0x84000000 | 0xbfe75 | 0x84000000 | 0xbfe76 | 0x84000000 | 0xbfe77
1 | way 3 | set 15 | @ 0x6e3c0 | 0x84000000 | 0xbfe78 | 0x84000000 | 0xbfe79 | 0x84000000 | 0xbfe7a | 0x84000000 | 0xbfe7b | 0x84000000 | 0xbfe7c | 0x84000000 | 0xbfe7d | 0x84000000 | 0xbfe7e | 0x84000000 | 0xbfe7f
1 | way 3 | set 16 | @ 0x96400 | 0x84000000 | 0xbfe80 | 0x84000000 | 0xbfe81 | 0x84000000 | 0xbfe82 | 0x84000000 | 0xbfe83 | 0x84000000 | 0xbfe84 | 0x84000000 | 0xbfe85 | 0x84000000 | 0xbfe86 | 0x84000000 | 0xbfe87
1 | way 3 | set 17 | @ 0x6e440 | 0x84000000 | 0xbfe88 | 0x84000000 | 0xbfe89 | 0x84000000 | 0xbfe8a | 0x84000000 | 0xbfe8b | 0x84000000 | 0xbfe8c | 0x84000000 | 0xbfe8d | 0x84000000 | 0xbfe8e | 0x84000000 | 0xbfe8f
1 | way 3 | set 18 | @ 0x96480 | 0x84000000 | 0xbfe90 | 0x84000000 | 0xbfe91 | 0x84000000 | 0xbfe92 | 0x84000000 | 0xbfe93 | 0x84000000 | 0xbfe94 | 0x84000000 | 0xbfe95 | 0x84000000 | 0xbfe96 | 0x84000000 | 0xbfe97
1 | way 3 | set 19 | @ 0x964c0 | 0x84000000 | 0xbfe98 | 0x84000000 | 0xbfe99 | 0x84000000 | 0xbfe9a | 0x84000000 | 0xbfe9b | 0x84000000 | 0xbfe9c | 0x84000000 | 0xbfe9d | 0x84000000 | 0xbfe9e | 0x84000000 | 0xbfe9f
1 | way 3 | set 20 | @ 0x6e500 | 0x84000000 | 0xbfea0 | 0x84000000 | 0xbfea1 | 0x84000000 | 0xbfea2 | 0x84000000 | 0xbfea3 | 0x84000000 | 0xbfea4 | 0x84000000 | 0xbfea5 | 0x84000000 | 0xbfea6 | 0x84000000 | 0xbfea7
1 | way 3 | set 21 | @ 0x96540 | 0x84000000 | 0xbfea8 | 0x84000000 | 0xbfea9 | 0x84000000 | 0xbfeaa | 0x84000000 | 0xbfeab | 0x84000000 | 0xbfeac | 0x84000000 | 0xbfead | 0x84000000 | 0xbfeae | 0x84000000 | 0xbfeaf
1 | way 3 | set 22 | @ 0x6e580 | 0x84000000 | 0xbfeb0 | 0x84000000 | 0xbfeb1 | 0x84000000 | 0xbfeb2 | 0x84000000 | 0xbfeb3 | 0x84000000 | 0xbfeb4 | 0x84000000 | 0xbfeb5 | 0x84000000 | 0xbfeb6 | 0x84000000 | 0xbfeb7
1 | way 3 | set 23 | @ 0x965c0 | 0x84000000 | 0xbfeb8 | 0x84000000 | 0xbfeb9 | 0x84000000 | 0xbfeba | 0x84000000 | 0xbfebb | 0x84000000 | 0xbfebc | 0x84000000 | 0xbfebd | 0x84000000 | 0xbfebe | 0x84000000 | 0xbfebf
1 | way 3 | set 24 | @ 0x6e600 | 0x84000000 | 0xbfec0 | 0x84000000 | 0xbfec1 | 0x84000000 | 0xbfec2 | 0x84000000 | 0xbfec3 | 0x84000000 | 0xbfec4 | 0x84000000 | 0xbfec5 | 0x84000000 | 0xbfec6 | 0x84000000 | 0xbfec7
1 | way 3 | set 25 | @ 0x6e640 | 0x84000000 | 0xbfec8 | 0x84000000 | 0xbfec9 | 0x84000000 | 0xbfeca | 0x84000000 | 0xbfecb | 0x84000000 | 0xbfecc | 0x84000000 | 0xbfecd | 0x84000000 | 0xbfece | 0x84000000 | 0xbfecf
1 | way 3 | set 26 | @ 0x6e680 | 0x84000000 | 0xbfed0 | 0x84000000 | 0xbfed1 | 0x84000000 | 0xbfed2 | 0x84000000 | 0xbfed3 | 0x84000000 | 0xbfed4 | 0x84000000 | 0xbfed5 | 0x84000000 | 0xbfed6 | 0x84000000 | 0xbfed7
1 | way 3 | set 27 | @ 0x6e6c0 | 0x84000000 | 0xbfed8 | 0x84000000 | 0xbfed9 | 0x84000000 | 0xbfeda | 0x84000000 | 0xbfedb | 0x84000000 | 0xbfedc | 0x84000000 | 0xbfedd | 0x84000000 | 0xbfede | 0x84000000 | 0xbfedf
1 | way 3 | set 28 | @ 0x96700 | 0x84000000 | 0xbfee0 | 0x84000000 | 0xbfee1 | 0x84000000 | 0xbfee2 | 0x84000000 | 0xbfee3 | 0x84000000 | 0xbfee4 | 0x84000000 | 0xbfee5 | 0x84000000 | 0xbfee6 | 0x84000000 | 0xbfee7
1 | way 3 | set 29 | @ 0x6e740 | 0x84000000 | 0xbfee8 | 0x84000000 | 0xbfee9 | 0x84000000 | 0xbfeea | 0x84000000 | 0xbfeeb | 0x84000000 | 0xbfeec | 0x84000000 | 0xbfeed | 0x84000000 | 0xbfeee | 0x84000000 | 0xbfeef
1 | way 3 | set 30 | @ 0x96780 | 0x84000000 | 0xbfef0 | 0x84000000 | 0xbfef1 | 0x84000000 | 0xbfef2 | 0x84000000 | 0xbfef3 | 0x84000000 | 0xbfef4 | 0x84000000 | 0xbfef5 | 0x84000000 | 0xbfef6 | 0x84000000 | 0xbfef7
1 | way 3 | set 31 | @ 0x137c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xc0000018 | 0xc000001a
1 | way 3 | set 32 | @ 0x97800 | 0x84000000 | 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 3 | set 33 | @ 0xba840 | 0x84000000 | 0xbfd08 | 0x84000000 | 0xbfd09 | 0x84000000 | 0xbfd0a | 0x84000000 | 0xbfd0b | 0x84000000 | 0xbfd0c | 0x84000000 | 0xbfd0d | 0x84000000 | 0xbfd0e | 0x84000000 | 0xbfd0f
1 | way 3 | set 34 | @ 0x96880 | 0x84000000 | 0xbff10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 3 | set 35 | @ 0x6f8c0 | 0x84000000 | 0xbfd18 | 0x84000000 | 0xbfd19 | 0x84000000 | 0xbfd1a | 0x84000000 | 0xbfd1b | 0x84000000 | 0xbfd1c | 0x84000000 | 0xbfd1d | 0x84000000 | 0xbfd1e | 0x84000000 | 0xbfd1f
1 | way 3 | set 36 | @ 0x1a900 | 0xa4400000 | 0xbff20 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 3 | set 37 | @ 0x6f940 | 0x84000000 | 0xbfd28 | 0x84000000 | 0xbfd29 | 0x84000000 | 0xbfd2a | 0x84000000 | 0xbfd2b | 0x84000000 | 0xbfd2c | 0x84000000 | 0xbfd2d | 0x84000000 | 0xbfd2e | 0x84000000 | 0xbfd2f
1 | way 3 | set 38 | @ 0xbfc04980 | 0xbfc02cf0 | 0xbfc02b28 | 0xbfc02c54 | 0xbfc02bc8 | 0x4f425b0a | 0x4520544f | 0x524f5252 | 0x694d205d | 0x6e697373 | 0x41522067 | 0x7370204d | 0x69206765 | 0x6c63206e | 0x65747375 | 0x2072 | 0x4f425b0a
1 | way 3 | set 39 | @ 0x6f9c0 | 0x84000000 | 0xbfd38 | 0x84000000 | 0xbfd39 | 0x84000000 | 0xbfd3a | 0x84000000 | 0xbfd3b | 0x84000000 | 0xbfd3c | 0x84000000 | 0xbfd3d | 0x84000000 | 0xbfd3e | 0x84000000 | 0xbfd3f
1 | way 3 | set 40 | @ 0x6fa00 | 0x84000000 | 0xbfd40 | 0x84000000 | 0xbfd41 | 0x84000000 | 0xbfd42 | 0x84000000 | 0xbfd43 | 0x84000000 | 0xbfd44 | 0x84000000 | 0xbfd45 | 0x84000000 | 0xbfd46 | 0x84000000 | 0xbfd47
1 | way 3 | set 41 | @ 0x6fa40 | 0x84000000 | 0xbfd48 | 0x84000000 | 0xbfd49 | 0x84000000 | 0xbfd4a | 0x84000000 | 0xbfd4b | 0x84000000 | 0xbfd4c | 0x84000000 | 0xbfd4d | 0x84000000 | 0xbfd4e | 0x84000000 | 0xbfd4f
1 | way 3 | set 42 | @ 0xbaa80 | 0x84000000 | 0xbfd50 | 0x84000000 | 0xbfd51 | 0x84000000 | 0xbfd52 | 0x84000000 | 0xbfd53 | 0x84000000 | 0xbfd54 | 0x84000000 | 0xbfd55 | 0x84000000 | 0xbfd56 | 0x84000000 | 0xbfd57
1 | way 3 | set 43 | @ 0x94ac0 | 0x84000000 | 0xbfd58 | 0x84000000 | 0xbfd59 | 0x84000000 | 0xbfd5a | 0x84000000 | 0xbfd5b | 0x84000000 | 0xbfd5c | 0x84000000 | 0xbfd5d | 0x84000000 | 0xbfd5e | 0x84000000 | 0xbfd5f
1 | way 3 | set 44 | @ 0x18b00 | 0x84000000 | 0xbfd60 | 0x84000000 | 0xbfd61 | 0x84000000 | 0xbfd62 | 0x84000000 | 0xbfd63 | 0x84000000 | 0xbfd64 | 0x84000000 | 0xbfd65 | 0x84000000 | 0xbfd66 | 0x84000000 | 0xbfd67
1 | way 3 | set 45 | @ 0x6fb40 | 0x84000000 | 0xbfd68 | 0x84000000 | 0xbfd69 | 0x84000000 | 0xbfd6a | 0x84000000 | 0xbfd6b | 0x84000000 | 0xbfd6c | 0x84000000 | 0xbfd6d | 0x84000000 | 0xbfd6e | 0x84000000 | 0xbfd6f
1 | way 3 | set 46 | @ 0x6fb80 | 0x84000000 | 0xbfd70 | 0x84000000 | 0xbfd71 | 0x84000000 | 0xbfd72 | 0x84000000 | 0xbfd73 | 0x84000000 | 0xbfd74 | 0x84000000 | 0xbfd75 | 0x84000000 | 0xbfd76 | 0x84000000 | 0xbfd77
1 | way 3 | set 47 | @ 0x94bc0 | 0x84000000 | 0xbfd78 | 0x84000000 | 0xbfd79 | 0x84000000 | 0xbfd7a | 0x84000000 | 0xbfd7b | 0x84000000 | 0xbfd7c | 0x84000000 | 0xbfd7d | 0x84000000 | 0xbfd7e | 0x84000000 | 0xbfd7f
1 | way 3 | set 48 | @ 0x6fc00 | 0x84000000 | 0xbfd80 | 0x84000000 | 0xbfd81 | 0x84000000 | 0xbfd82 | 0x84000000 | 0xbfd83 | 0x84000000 | 0xbfd84 | 0x84000000 | 0xbfd85 | 0x84000000 | 0xbfd86 | 0x84000000 | 0xbfd87
1 | way 3 | set 49 | @ 0xbac40 | 0x84000000 | 0xbfd88 | 0x84000000 | 0xbfd89 | 0x84000000 | 0xbfd8a | 0x84000000 | 0xbfd8b | 0x84000000 | 0xbfd8c | 0x84000000 | 0xbfd8d | 0x84000000 | 0xbfd8e | 0x84000000 | 0xbfd8f
1 | way 3 | set 50 | @ 0xbfc0dc80 | 0 | 0 | 0 | 0 | 0 | 0x1a8 | 0 | 0x800000 | 0xb0000 | 0 | 0x65646f63 | 0 | 0 | 0 | 0 | 0
1 | way 3 | set 51 | @ 0xbacc0 | 0x84000000 | 0xbfd98 | 0x84000000 | 0xbfd99 | 0x84000000 | 0xbfd9a | 0x84000000 | 0xbfd9b | 0x84000000 | 0xbfd9c | 0x84000000 | 0xbfd9d | 0x84000000 | 0xbfd9e | 0x84000000 | 0xbfd9f
1 | way 3 | set 52 | @ 0xbcd00 | 0x84000000 | 0xbffa0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 3 | set 53 | @ 0x94d40 | 0x84000000 | 0xbfda8 | 0x84000000 | 0xbfda9 | 0x84000000 | 0xbfdaa | 0x84000000 | 0xbfdab | 0x84000000 | 0xbfdac | 0x84000000 | 0xbfdad | 0x84000000 | 0xbfdae | 0x84000000 | 0xbfdaf
1 | way 3 | set 54 | @ 0x6fd80 | 0x84000000 | 0xbfdb0 | 0x84000000 | 0xbfdb1 | 0x84000000 | 0xbfdb2 | 0x84000000 | 0xbfdb3 | 0x84000000 | 0xbfdb4 | 0x84000000 | 0xbfdb5 | 0x84000000 | 0xbfdb6 | 0x84000000 | 0xbfdb7
1 | way 3 | set 55 | @ 0x94dc0 | 0x84000000 | 0xbfdb8 | 0x84000000 | 0xbfdb9 | 0x84000000 | 0xbfdba | 0x84000000 | 0xbfdbb | 0x84000000 | 0xbfdbc | 0x84000000 | 0xbfdbd | 0x84000000 | 0xbfdbe | 0x84000000 | 0xbfdbf
1 | way 3 | set 56 | @ 0x6fe00 | 0x84000000 | 0xbfdc0 | 0x84000000 | 0xbfdc1 | 0x84000000 | 0xbfdc2 | 0x84000000 | 0xbfdc3 | 0x84000000 | 0xbfdc4 | 0x84000000 | 0xbfdc5 | 0x84000000 | 0xbfdc6 | 0x84000000 | 0xbfdc7
1 | way 3 | set 57 | @ 0xbae40 | 0x84000000 | 0xbfdc8 | 0x84000000 | 0xbfdc9 | 0x84000000 | 0xbfdca | 0x84000000 | 0xbfdcb | 0x84000000 | 0xbfdcc | 0x84000000 | 0xbfdcd | 0x84000000 | 0xbfdce | 0x84000000 | 0xbfdcf
1 | way 3 | set 58 | @ 0x94e80 | 0x84000000 | 0xbfdd0 | 0x84000000 | 0xbfdd1 | 0x84000000 | 0xbfdd2 | 0x84000000 | 0xbfdd3 | 0x84000000 | 0xbfdd4 | 0x84000000 | 0xbfdd5 | 0x84000000 | 0xbfdd6 | 0x84000000 | 0xbfdd7
1 | way 3 | set 59 | @ 0x94ec0 | 0x84000000 | 0xbfdd8 | 0x84000000 | 0xbfdd9 | 0x84000000 | 0xbfdda | 0x84000000 | 0xbfddb | 0x84000000 | 0xbfddc | 0x84000000 | 0xbfddd | 0x84000000 | 0xbfdde | 0x84000000 | 0xbfddf
1 | way 3 | set 60 | @ 0xf00 | 0x1 | 0 | 0x101 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x3 | 0x10003 | 0x20003 | 0x30003 | 0x40003 | 0x50003
1 | way 3 | set 61 | @ 0xbfc0df40 | 0 | 0x2 | 0x3 | 0xffffffff | 0 | 0x1 | 0 | 0 | 0 | 0x6e69616d | 0 | 0 | 0 | 0 | 0 | 0
1 | way 3 | set 62 | @ 0xbdf80 | 0x84000000 | 0xff0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 3 | set 63 | @ 0x6ffc0 | 0x84000000 | 0xbfdf8 | 0x84000000 | 0xbfdf9 | 0x84000000 | 0xbfdfa | 0x84000000 | 0xbfdfb | 0x84000000 | 0xbfdfc | 0x84000000 | 0xbfdfd | 0x84000000 | 0xbfdfe | 0x84000000 | 0xbfdff
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_IDLE> Read request: srcid = 3 / address = 0x18000 / pktid = 0x1 / nwords = 16
****************** cycle 1701061 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0xd
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
****************** cycle 1701062 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 1 / set = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_LOCK> Accessing directory:  address = 0x18000 / hit = 1 / count = 1 / is_cnt = 0
****************** cycle 1701063 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_REQ> Requesting HEAP lock 
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 0
****************** cycle 1701064 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_LOCK> Update directory: tag = 0x6 set = 0 way = 1 count = 2 is_cnt = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 1
****************** cycle 1701065 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_WRITE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_WRITE> Add an entry in the heap: owner_id = 3 owner_ins = 0
****************** cycle 1701066 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 1
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 2
****************** cycle 1701067 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 2
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d0 / for address 0x000019480
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 3
****************** cycle 1701068 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 3
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019480 srcid = 0d0 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 4
****************** cycle 1701069 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 4
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019480 srcid = 0d0 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 0 addr = 0x19480 wdata = 0x8a000000 eop = 0 cpt  = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 5
****************** cycle 1701070 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 5
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 0 addr = 0x19480 wdata = 0xaa000000 eop = 1 cpt  = 1
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 6
****************** cycle 1701071 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 6
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 7
****************** cycle 1701072 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 7
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 8
****************** cycle 1701073 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 8
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19480 / hit = 1 / count = 1 / is_cnt = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 9
****************** cycle 1701074 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 9
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 10
****************** cycle 1701075 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 10
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 2315255808 / actual value = 2315255808 / forced_fail = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 11
****************** cycle 1701076 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_DIR_HIT_WRITE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 11
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 12
****************** cycle 1701077 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_UPT_LOCK | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 12
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 13
****************** cycle 1701078 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_UPT_LOCK | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 31 / WORD = 13
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_UPT_LOCK> Register multi-update transaction in UPT / wok = 1 / nline  = 0x00000000652 / count = 0x1
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0xc0000018 / cpt = 14
****************** cycle 1701079 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_UPT_HEAP_LOCK | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xc0000018 / WAY = 0 / SET = 31 / WORD = 14
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0xc000001a / cpt = 15
****************** cycle 1701080 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_RSP | WRITE_IDLE | CAS_UPT_HEAP_LOCK | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xc000001a / WAY = 0 / SET = 31 / WORD = 15
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_RSP> Request the TGT_RSP FSM to return data: rsrcid = 3 / address = 0x18000 / nwords = 16
  <MEMC memc_0_0.CAS_UPT_HEAP_LOCK> Get access to the heap
****************** cycle 1701081 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DIR_UPDT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_UPT_REQ | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DIR_UPDT> Switch slot to VALID state PADDR = 0x0000137f8 / WAY = 0 / SET = 31
1 | way 0 | set 0 | @ 0xbfc0c000 | 0xbabef00d | 0x1 | 0x1 | 0x1 | 0xf | 0x4 | 0 | 0 | 0 | 0 | 0xb | 0x24 | 0x25 | 0x7 | 0x4 | 0x1c
0 | way 0 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 31 | @ 0x137c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xc0000018 | 0xc000001a
0 | way 0 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 61 | @ 0xbfc04f40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x1000 | 0x2000
1 | way 0 | set 62 | @ 0xbfc04f80 | 0x3000 | 0x12000 | 0x68000 | 0x8e000 | 0xb4000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 0 | @ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 0 | @ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 0 | @ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_IDLE> Read request: srcid = 1 / address = 0x18000 / pktid = 0x1 / nwords = 16
  <MEMC memc_0_0.CAS_UPT_REQ> Send the first update request to CC_SEND FSM  / address = 0x19480 / wdata = 0xaa000000 / srcid = 0 / inst = 0
****************** cycle 1701082 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_TLB_PTE1_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2.DCACHE_TLB_PTE1_GET> HIT in dcache / paddr = 0x0000137f8 / way = 0 / set = 31 / word = 14 / PTD = 0xc0000018
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
****************** cycle 1701083 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_HEADER | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_TLB_PTE2_GET> MISS in dcache: PTE address = 0x000018000
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
****************** cycle 1701084 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_SELECT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_SELECT> Select a slot: / WAY = 1 / SET = 0 / PADDR = 0x000018000
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_LOCK> Accessing directory:  address = 0x18000 / hit = 1 / count = 2 / is_cnt = 0
  <MEMC memc_0_0.CC_SEND_CAS_UPDT_NLINE> Multicast-Update for line 0d1618
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0xae000000 / cpt = 0
****************** cycle 1701085 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_DATA_MISS | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_DATA | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_REQ> Requesting HEAP lock 
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc00 / cpt = 1
****************** cycle 1701086 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_DATA_MISS | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_HEADER | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xae000000 / WAY = 1 / SET = 0 / WORD = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d2 / for address 0x000018000
  <MEMC memc_0_0.READ_HEAP_REQ> Requesting HEAP lock 
****************** cycle 1701087 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_DATA_MISS | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_READ | TGT_RSP_READ | READ_HEAP_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc00 / WAY = 1 / SET = 0 / WORD = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_READ> Push into read_fifo: address = 0x000018000 srcid = 0d2 trdid = 0d0 pktid = 0d1 plen = 0d64
  <MEMC memc_0_0.READ_HEAP_LOCK> Update directory: tag = 0x6 set = 0 way = 1 count = 3 is_cnt = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0x8e000000 / cpt = 2
****************** cycle 1701088 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_WRITE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x8e000000 / WAY = 1 / SET = 0 / WORD = 2
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_WRITE> Add an entry in the heap: owner_id = 1 owner_ins = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc01 / cpt = 3
****************** cycle 1701089 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc01 / WAY = 1 / SET = 0 / WORD = 3
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0x8e000000 / cpt = 4
****************** cycle 1701090 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_CC_CHECK> paddr = 0x000019480 r_dcache_vci_paddr = 0x000019480 mask = 0x0ffffffc0 (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) = 0 (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT) = 0 ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) = 0x1
  <PROC proc_0_0_0 DCACHE_CC_CHECK> Coherence request received: PADDR = 0x000019480 / TYPE = 3 / HIT = 1
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 2382364672 / WAY = 1 / SET = 0 / WORD = 4
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc02 / cpt = 5
****************** cycle 1701091 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc02 / WAY = 1 / SET = 0 / WORD = 5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0xae000000 / cpt = 6
****************** cycle 1701092 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xae000000 / WAY = 1 / SET = 0 / WORD = 6
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc03 / cpt = 7
****************** cycle 1701093 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc03 / WAY = 1 / SET = 0 / WORD = 7
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0xae400000 / cpt = 8
****************** cycle 1701094 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xae400000 / WAY = 1 / SET = 0 / WORD = 8
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc04 / cpt = 9
****************** cycle 1701095 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc04 / WAY = 1 / SET = 0 / WORD = 9
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0x8e000000 / cpt = 10
****************** cycle 1701096 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x8e000000 / WAY = 1 / SET = 0 / WORD = 10
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc05 / cpt = 11
****************** cycle 1701097 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc05 / WAY = 1 / SET = 0 / WORD = 11
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 12
****************** cycle 1701098 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 1 / SET = 0 / WORD = 12
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 13
****************** cycle 1701099 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 1 / SET = 0 / WORD = 13
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 14
****************** cycle 1701100 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_CC_UPDT> Write one word / WAY = 1 / SET = 18 / WORD = 0 / VALUE = 0xaa000000
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 1 / SET = 0 / WORD = 14
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 15
****************** cycle 1701101 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 1 / SET = 0 / WORD = 15
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_RSP> Request the TGT_RSP FSM to return data: rsrcid = 1 / address = 0x18000 / nwords = 16
****************** cycle 1701102 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DIR_UPDT> Switch slot to VALID state PADDR = 0x000018000 / WAY = 1 / SET = 0
1 | way 0 | set 0 | @ 0xbfc0c000 | 0xbabef00d | 0x1 | 0x1 | 0x1 | 0xf | 0x4 | 0 | 0 | 0 | 0 | 0xb | 0x24 | 0x25 | 0x7 | 0x4 | 0x1c
0 | way 0 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 31 | @ 0x137c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xc0000018 | 0xc000001a
0 | way 0 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 62 | @ 0xbfc04f80 | 0x3000 | 0x12000 | 0x68000 | 0x8e000 | 0xb4000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 0 | @ 0x18000 | 0xae000000 | 0xbfc00 | 0x8e000000 | 0xbfc01 | 0x8e000000 | 0xbfc02 | 0xae000000 | 0xbfc03 | 0xae400000 | 0xbfc04 | 0x8e000000 | 0xbfc05 | 0 | 0 | 0 | 0
0 | way 1 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 0 | @ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 0 | @ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_IDLE> Read request: srcid = 2 / address = 0x18000 / pktid = 0x1 / nwords = 16
****************** cycle 1701103 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0xae000000 PTE_PPN = 0xbfc00
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
****************** cycle 1701104 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_LOCK> Accessing directory:  address = 0x18000 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1701105 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_MULTI_ACK | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB / set = 0 / way = 0
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
     [0] [0]   [1][1][0][1][1][1][0][0][0][0][1][0x17f80][  0xbfc00][0x000000600]
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_REQ> Requesting HEAP lock 
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0xae000000 / cpt = 0
****************** cycle 1701106 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.MULTI_ACK_IDLE> Response for UPT entry 
  <MEMC memc_0_0.READ_HEAP_LOCK> Update directory: tag = 0x6 set = 0 way = 1 count = 4 is_cnt = 1
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc00 / cpt = 1
****************** cycle 1701107 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_ERASE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_UPT_LOCK | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xae000000 / WAY = 1 / SET = 0 / WORD = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701108 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_LAST | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_UPT_LOCK | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc00 / WAY = 1 / SET = 0 / WORD = 1
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.MULTI_ACK_UPT_LOCK> Decrement the responses counter for UPT: entry = 0 / rsp_count = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0x8e000000 / cpt = 2
****************** cycle 1701109 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_UPT_CLEAR | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x8e000000 / WAY = 1 / SET = 0 / WORD = 2
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.MULTI_ACK_UPT_CLEAR> Clear UPT entry 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc01 / cpt = 3
****************** cycle 1701110 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_WRITE_RSP | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc01 / WAY = 1 / SET = 0 / WORD = 3
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.MULTI_ACK_WRITE_RSP> Request TGT_RSP FSM to send a response to srcid 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0x8e000000 / cpt = 4
****************** cycle 1701111 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x8e000000 / WAY = 1 / SET = 0 / WORD = 4
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc02 / cpt = 5
****************** cycle 1701112 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc02 / WAY = 1 / SET = 0 / WORD = 5
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0xae000000 / cpt = 6
****************** cycle 1701113 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xae000000 / WAY = 1 / SET = 0 / WORD = 6
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x80090000 / BYPASS = 0 / PTE_ADR = 0x000013000
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc03 / cpt = 7
****************** cycle 1701114 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc03 / WAY = 1 / SET = 0 / WORD = 7
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE1_GET> MISS in dcache: PTE1 address = 0x000013000
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0xae400000 / cpt = 8
****************** cycle 1701115 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xae400000 / WAY = 1 / SET = 0 / WORD = 8
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_SELECT> Select a slot: / WAY = 2 / SET = 0 / PADDR = 0x000013000
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc04 / cpt = 9
****************** cycle 1701116 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc04 / WAY = 1 / SET = 0 / WORD = 9
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0x8e000000 / cpt = 10
****************** cycle 1701117 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x8e000000 / WAY = 1 / SET = 0 / WORD = 10
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000013000
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc05 / cpt = 11
****************** cycle 1701118 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_READ | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc05 / WAY = 1 / SET = 0 / WORD = 11
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_READ> Push into read_fifo: address = 0x000013000 srcid = 0d3 trdid = 0d0 pktid = 0d1 plen = 0d64
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 12
****************** cycle 1701119 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 1 / SET = 0 / WORD = 12
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 13
****************** cycle 1701120 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 1 / SET = 0 / WORD = 13
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 14
****************** cycle 1701121 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 1 / SET = 0 / WORD = 14
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 15
****************** cycle 1701122 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 1 / SET = 0 / WORD = 15
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_RSP> Request the TGT_RSP FSM to return data: rsrcid = 2 / address = 0x18000 / nwords = 16
****************** cycle 1701123 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DIR_UPDT> Switch slot to VALID state PADDR = 0x000018000 / WAY = 1 / SET = 0
1 | way 0 | set 0 | @ 0xbfc0c000 | 0xbabef00d | 0x1 | 0x1 | 0x1 | 0xf | 0x4 | 0 | 0 | 0 | 0 | 0xb | 0x24 | 0x25 | 0x7 | 0x4 | 0x1c
0 | way 0 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 31 | @ 0x137c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xc0000018 | 0xc000001a
0 | way 0 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 61 | @ 0xbfc04f40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x1000 | 0x2000
1 | way 0 | set 62 | @ 0xbfc04f80 | 0x3000 | 0x12000 | 0x68000 | 0x8e000 | 0xb4000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 0 | @ 0x18000 | 0xae000000 | 0xbfc00 | 0x8e000000 | 0xbfc01 | 0x8e000000 | 0xbfc02 | 0xae000000 | 0xbfc03 | 0xae400000 | 0xbfc04 | 0x8e000000 | 0xbfc05 | 0 | 0 | 0 | 0
0 | way 1 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 0 | @ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 0 | @ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_IDLE> Read request: srcid = 3 / address = 0x13000 / pktid = 0x1 / nwords = 16
****************** cycle 1701124 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT | READ_DIR_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0xae000000 PTE_PPN = 0xbfc00
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
****************** cycle 1701125 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT | READ_DIR_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_LOCK> Accessing directory:  address = 0x13000 / hit = 1 / count = 1 / is_cnt = 0
  <MEMC memc_0_0.TGT_RSP_INIT> Write response after coherence transaction / rsrcid = 0 / rtrdid = 0 / rpktid = 5
****************** cycle 1701126 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_HEAP_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB / set = 0 / way = 0
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
     [0] [0]   [1][1][0][1][1][1][0][0][0][0][1][0x17f80][  0xbfc00][0x000000600]
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_REQ> Requesting HEAP lock 
****************** cycle 1701127 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_LOCK> Update directory: tag = 0x4 set = 192 way = 0 count = 2 is_cnt = 0
****************** cycle 1701128 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_WRITE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_WRITE> Add an entry in the heap: owner_id = 0x3 owner_ins = 0
****************** cycle 1701129 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0xae000000 / cpt = 0
****************** cycle 1701130 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc00 / cpt = 1
****************** cycle 1701131 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x80090000 / BYPASS = 0x1 / PTE_ADR = 0x000019480
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xae000000 / WAY = 1 / SET = 0 / WORD = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701132 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0xaa000000 PTE_PPN = 0xd
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc00 / WAY = 1 / SET = 0 / WORD = 1
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0x8e000000 / cpt = 2
****************** cycle 1701133 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 1 / set = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 2382364672 / WAY = 1 / SET = 0 / WORD = 2
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc01 / cpt = 3
****************** cycle 1701134 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB / set = 0 / way = 1
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
     [0] [0]   [1][1][0][1][1][1][0][0][0][0][1][0x17f80][  0xbfc00][0x000000600]
     [0] [1]   [1][1][0][1][0][1][0][0][0][0][1][0x10012][      0xd][0x000000652]
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x80090000 / BYPASS = 0 / PTE_ADR = 0x000013000
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc01 / WAY = 1 / SET = 0 / WORD = 3
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0x8e000000 / cpt = 4
****************** cycle 1701135 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1.DCACHE_TLB_PTE1_GET> MISS in dcache: PTE1 address = 0x000013000
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x8e000000 / WAY = 1 / SET = 0 / WORD = 4
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc02 / cpt = 5
****************** cycle 1701136 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_SELECT> Select a slot: / WAY = 2 / SET = 0 / PADDR = 0x000013000
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc02 / WAY = 1 / SET = 0 / WORD = 5
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0xae000000 / cpt = 6
****************** cycle 1701137 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xae000000 / WAY = 1 / SET = 0 / WORD = 6
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc03 / cpt = 7
****************** cycle 1701138 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 ICACHE_MISS_SELECT> Select a slot: / WAY = 1 / SET = 0 / VICTIM = 0x002ff0080
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc03 / WAY = 1 / SET = 0 / WORD = 7
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d1 / for address 0x000013000
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0xae400000 / cpt = 8
****************** cycle 1701139 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_READ | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 ICACHE_MISS_CLEAN> Switch to ZOMBI state / WAY = 1 / SET = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 2923429888 / WAY = 1 / SET = 0 / WORD = 8
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_READ> Push into read_fifo: address = 0x000013000 srcid = 0d1 trdid = 0d0 pktid = 0d1 plen = 0d64
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc04 / cpt = 9
****************** cycle 1701140 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_dcache_cc_send_nline = 0x000002ed2
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc04 / WAY = 1 / SET = 0 / WORD = 9
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0x8e000000 / cpt = 10
****************** cycle 1701141 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_dcache_cc_send_nline = 0x000002ed2
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x8e000000 / WAY = 1 / SET = 0 / WORD = 10
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d0 / for address 0x00000d000
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc05 / cpt = 11
****************** cycle 1701142 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_READ | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc05 / WAY = 1 / SET = 0 / WORD = 11
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_READ> Push into read_fifo: address = 0x00000d000 srcid = 0d0 trdid = 0d0 pktid = 0d3 plen = 0d64
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 12
****************** cycle 1701143 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_CLEANUP | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 1 / SET = 0 / WORD = 12
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 13
****************** cycle 1701144 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_CLEANUP | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 1 / SET = 0 / WORD = 13
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CLEANUP_IDLE> Cleanup request: / owner_id = 0 / owner_ins = 0x1
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 14
****************** cycle 1701145 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_GET_NLINE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 1 / SET = 0 / WORD = 14
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CLEANUP_GET_NLINE> Cleanup request: / address = 0xbfc02000
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 15
****************** cycle 1701146 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_DIR_REQ
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 1 / SET = 0 / WORD = 15
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_RSP> Request the TGT_RSP FSM to return data: rsrcid = 3 / address = 0x13000 / nwords = 16
****************** cycle 1701147 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DIR_UPDT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_DIR_REQ
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DIR_UPDT> Switch slot to VALID state PADDR = 0x000018000 / WAY = 1 / SET = 0
1 | way 0 | set 0 | @ 0xbfc0c000 | 0xbabef00d | 0x1 | 0x1 | 0x1 | 0xf | 0x4 | 0 | 0 | 0 | 0 | 0xb | 0x24 | 0x25 | 0x7 | 0x4 | 0x1c
0 | way 0 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 31 | @ 0x137c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xc0000018 | 0xc000001a
0 | way 0 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 61 | @ 0xbfc04f40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x1000 | 0x2000
1 | way 0 | set 62 | @ 0xbfc04f80 | 0x3000 | 0x12000 | 0x68000 | 0x8e000 | 0xb4000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 0 | @ 0x18000 | 0xae000000 | 0xbfc00 | 0x8e000000 | 0xbfc01 | 0x8e000000 | 0xbfc02 | 0xae000000 | 0xbfc03 | 0xae400000 | 0xbfc04 | 0x8e000000 | 0xbfc05 | 0 | 0 | 0 | 0
0 | way 1 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 0 | @ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 0 | @ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_IDLE> Read request: srcid = 1 / address = 0x13000 / pktid = 0x1 / nwords = 16
  <MEMC memc_0_0.CLEANUP_DIR_REQ> Requesting DIR lock 
****************** cycle 1701148 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_DIR_LOCK
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0xae000000 PTE_PPN = 0xbfc00
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.CLEANUP_DIR_LOCK> Test directory status:  line = 0x000bfc02000 / hit = 0 / dir_id = 0 / dir_ins = 0 / search_id = 0 / search_ins = 0x1 / count = 0 / is_cnt = 0
****************** cycle 1701149 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_TLB_PTE2_SELECT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_UPT_LOCK
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
****************** cycle 1701150 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_TLB_PTE2_UPDT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_UPT_LOCK
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB / set = 0 / way = 0
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
     [0] [0]   [1][1][0][1][1][1][0][0][0][0][1][0x17f80][  0xbfc00][0x000000600]
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.CLEANUP_UPT_LOCK> Unexpected cleanup with no corresponding UPT entry: address = 0xbfc02000
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0xc0000019 / cpt = 0
****************** cycle 1701151 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_TLB_RETURN | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_SEND_ACK
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_LOCK> Accessing directory:  address = 0x13000 / hit = 1 / count = 2 / is_cnt = 0
  <MEMC memc_0_0.CLEANUP_SEND_ACK> Send the response to a cleanup request: srcid = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 1
****************** cycle 1701152 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xc0000019 / WAY = 2 / SET = 0 / WORD = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_REQ> Requesting HEAP lock 
****************** cycle 1701153 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_ACK | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_LOCK> Update directory: tag = 0x4 set = 192 way = 0 count = 3 is_cnt = 0
  <MEMC memc_0_0.CC_SEND_CLEANUP_ACK> Cleanup Acknowledgement for srcid 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 2
****************** cycle 1701154 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005a8>
  <InsRsp    valid no error ins 0x275a0000>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_WRITE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 2
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_WRITE> Add an entry in the heap: owner_id = 1 owner_ins = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 3
****************** cycle 1701155 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005ac>
  <InsRsp    valid no error ins 0x3400008>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 3
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 4
****************** cycle 1701156 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0xbfc005b0>
  <InsRsp    valid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 4
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 5
****************** cycle 1701157 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 6
****************** cycle 1701158 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_TLB_MISS | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 ICACHE_CC_CHECK>  CC_TYPE_CLACK slot returns to empty state set = 0 / way = 0x1
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x80090000 / BYPASS = 0 / PTE_ADR = 0x000013000
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 6
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 7
****************** cycle 1701159 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_TLB_PTE1_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2.DCACHE_TLB_PTE1_GET> MISS in dcache: PTE1 address = 0x000013000
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 7
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 8
****************** cycle 1701160 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_SELECT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_SELECT> Select a slot: / WAY = 2 / SET = 0 / PADDR = 0x000013000
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 8
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 9
****************** cycle 1701161 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_DATA_MISS | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 9
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 10
****************** cycle 1701162 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_DATA_MISS | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 10
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d2 / for address 0x000013000
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 11
****************** cycle 1701163 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_DATA_MISS | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_READ | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 11
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_READ> Push into read_fifo: address = 0x000013000 srcid = 0d2 trdid = 0d0 pktid = 0d1 plen = 0d64
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 12
****************** cycle 1701164 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 12
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 13
****************** cycle 1701165 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 13
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 14
****************** cycle 1701166 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 14
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 15
****************** cycle 1701167 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 15
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_RSP> Request the TGT_RSP FSM to return data: rsrcid = 1 / address = 0x13000 / nwords = 16
****************** cycle 1701168 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DIR_UPDT> Switch slot to VALID state PADDR = 0x000013000 / WAY = 2 / SET = 0
1 | way 0 | set 0 | @ 0xbfc0c000 | 0xbabef00d | 0x1 | 0x1 | 0x1 | 0xf | 0x4 | 0 | 0 | 0 | 0 | 0xb | 0x24 | 0x25 | 0x7 | 0x4 | 0x1c
0 | way 0 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 31 | @ 0x137c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xc0000018 | 0xc000001a
0 | way 0 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 62 | @ 0xbfc04f80 | 0x3000 | 0x12000 | 0x68000 | 0x8e000 | 0xb4000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 0 | @ 0x18000 | 0xae000000 | 0xbfc00 | 0x8e000000 | 0xbfc01 | 0x8e000000 | 0xbfc02 | 0xae000000 | 0xbfc03 | 0xae400000 | 0xbfc04 | 0x8e000000 | 0xbfc05 | 0 | 0 | 0 | 0
0 | way 1 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 0 | @ 0x13000 | 0xc0000019 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 0 | @ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_IDLE> Read request: srcid = 0 / address = 0xd000 / pktid = 0x3 / nwords = 16
****************** cycle 1701169 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE1_GET> HIT in dcache / paddr = 0x000013000 / way = 2 / set = 0 / word = 0 / PTD = 0xc0000019
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
****************** cycle 1701170 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_GET> MISS in dcache: PTE address = 0x000019480
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_LOCK> Accessing directory:  address = 0xd000 / hit = 0 / count = 0 / is_cnt = 0
****************** cycle 1701171 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_TRT_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_SELECT> Select a slot: / WAY = 0 / SET = 18 / PADDR = 0x000019480
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0xc0000019 / cpt = 0
****************** cycle 1701172 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_TRT_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_TRT_LOCK> Check TRT: hit_read = 0 / hit_write = 0 / full = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 1
****************** cycle 1701173 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_TRT_SET | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xc0000019 / WAY = 2 / SET = 0 / WORD = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019480
  <MEMC memc_0_0.READ_TRT_SET> Write in Transaction Table:  address = 0xd000 / srcid = 0
****************** cycle 1701174 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_READ | TGT_RSP_READ | READ_TRT_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 1
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_READ> Push into read_fifo: address = 0x000019480 srcid = 0d3 trdid = 0d0 pktid = 0d1 plen = 0d64
  <MEMC memc_0_0.READ_TRT_REQ> Request GET transaction for address 0xd000
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 2
****************** cycle 1701175 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_WRITE_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 2
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_IDLE> Read request: srcid = 2 / address = 0x13000 / pktid = 0x1 / nwords = 16
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 3
****************** cycle 1701176 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_NLINE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 3
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.IXR_CMD_READ_NLINE> Send a get request to xram
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 4
****************** cycle 1701177 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 4
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_LOCK> Accessing directory:  address = 0x13000 / hit = 1 / count = 3 / is_cnt = 0
  <MEMC memc_0_0.IXR_RSP_IDLE> Response from XRAM to a get transaction
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 5
****************** cycle 1701178 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 5
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_REQ> Requesting HEAP lock 
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 6
****************** cycle 1701179 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 6
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_LOCK> Update directory: tag = 0x4 set = 192 way = 0 count = 4 is_cnt = 1
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 0 / data = 0x27bdff98
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 7
****************** cycle 1701180 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_ERASE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 7
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 1 / data = 0xafbf0064
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 8
****************** cycle 1701181 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_LAST | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 8
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 2 / data = 0xafbe0060
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 9
****************** cycle 1701182 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 9
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 3 / data = 0x3a0f021
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 10
****************** cycle 1701183 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 10
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 4 / data = 0xc0001c3
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 11
****************** cycle 1701184 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 11
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 5 / data = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 12
****************** cycle 1701185 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 12
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 6 / data = 0xafc2005c
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 13
****************** cycle 1701186 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 13
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 7 / data = 0x8fc2005c
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 14
****************** cycle 1701187 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 14
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 8 / data = 0x21082
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 15
****************** cycle 1701188 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 15
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_RSP> Request the TGT_RSP FSM to return data: rsrcid = 2 / address = 0x13000 / nwords = 16
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 9 / data = 0xafc20058
****************** cycle 1701189 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DIR_UPDT> Switch slot to VALID state PADDR = 0x000013000 / WAY = 2 / SET = 0
1 | way 0 | set 0 | @ 0xbfc0c000 | 0xbabef00d | 0x1 | 0x1 | 0x1 | 0xf | 0x4 | 0 | 0 | 0 | 0 | 0xb | 0x24 | 0x25 | 0x7 | 0x4 | 0x1c
0 | way 0 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 31 | @ 0x137c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xc0000018 | 0xc000001a
0 | way 0 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 61 | @ 0xbfc04f40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x1000 | 0x2000
1 | way 0 | set 62 | @ 0xbfc04f80 | 0x3000 | 0x12000 | 0x68000 | 0x8e000 | 0xb4000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 0 | @ 0x18000 | 0xae000000 | 0xbfc00 | 0x8e000000 | 0xbfc01 | 0x8e000000 | 0xbfc02 | 0xae000000 | 0xbfc03 | 0xae400000 | 0xbfc04 | 0x8e000000 | 0xbfc05 | 0 | 0 | 0 | 0
0 | way 1 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 0 | @ 0x13000 | 0xc0000019 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 0 | @ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_IDLE> Read request: srcid = 3 / address = 0x19480 / pktid = 0x1 / nwords = 16
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 10 / data = 0x8fc2005c
****************** cycle 1701190 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1.DCACHE_TLB_PTE1_GET> HIT in dcache / paddr = 0x000013000 / way = 2 / set = 0 / word = 0 / PTD = 0xc0000019
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 11 / data = 0x30420003
****************** cycle 1701191 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_TLB_PTE2_GET> MISS in dcache: PTE address = 0x000019480
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_LOCK> Accessing directory:  address = 0x19480 / hit = 1 / count = 1 / is_cnt = 0
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 12 / data = 0xc0004f1
****************** cycle 1701192 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_SELECT> Select a slot: / WAY = 0 / SET = 18 / PADDR = 0x000019480
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_REQ> Requesting HEAP lock 
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 13 / data = 0xafc20054
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0xc0000019 / cpt = 0
****************** cycle 1701193 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_LOCK> Update directory: tag = 0x6 set = 82 way = 0 count = 2 is_cnt = 0
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 14 / data = 0xc000342
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 1
****************** cycle 1701194 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_WRITE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xc0000019 / WAY = 2 / SET = 0 / WORD = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d1 / for address 0x000019480
  <MEMC memc_0_0.READ_HEAP_WRITE> Add an entry in the heap: owner_id = 0x3 owner_ins = 0
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 15 / data = 0xafc20050
****************** cycle 1701195 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_READ | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 1
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_READ> Push into read_fifo: address = 0x000019480 srcid = 0d1 trdid = 0d0 pktid = 0d1 plen = 0d64
  <MEMC memc_0_0.XRAM_RSP_IDLE> Available cache line in TRT: index = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 2
****************** cycle 1701196 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 2
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 3
****************** cycle 1701197 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 3
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 4
****************** cycle 1701198 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 4
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.XRAM_RSP_DIR_LOCK> Get access to directory
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 5
****************** cycle 1701199 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_TRT_COPY
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 5
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.XRAM_RSP_TRT_COPY> Select a slot:  way = 7 / set = 64 / inval_required = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 6
****************** cycle 1701200 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_INVAL_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 6
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 7
****************** cycle 1701201 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_INVAL_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 7
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.XRAM_RSP_INVAL_LOCK> Get acces to UPT
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 8
****************** cycle 1701202 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_UPDT
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 8
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.XRAM_RSP_DIR_UPDT> Directory update:  way = 7 / set = 64 / owner_id = 0 / owner_ins = 1 / count = 1 / is_cnt = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 9
****************** cycle 1701203 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_RSP
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 9
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.XRAM_RSP_DIR_RSP> Request the TGT_RSP FSM to return data: rsrcid = 0 / address = 0xd000 / nwords = 16
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 10
****************** cycle 1701204 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 10
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 11
****************** cycle 1701205 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 11
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 12
****************** cycle 1701206 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 12
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 13
****************** cycle 1701207 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 13
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 14
****************** cycle 1701208 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 14
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 15
****************** cycle 1701209 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 15
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_RSP> Request the TGT_RSP FSM to return data: rsrcid = 3 / address = 0x19480 / nwords = 16
****************** cycle 1701210 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DIR_UPDT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DIR_UPDT> Switch slot to VALID state PADDR = 0x000013000 / WAY = 2 / SET = 0
1 | way 0 | set 0 | @ 0xbfc0c000 | 0xbabef00d | 0x1 | 0x1 | 0x1 | 0xf | 0x4 | 0 | 0 | 0 | 0 | 0xb | 0x24 | 0x25 | 0x7 | 0x4 | 0x1c
0 | way 0 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 31 | @ 0x137c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xc0000018 | 0xc000001a
0 | way 0 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 61 | @ 0xbfc04f40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x1000 | 0x2000
1 | way 0 | set 62 | @ 0xbfc04f80 | 0x3000 | 0x12000 | 0x68000 | 0x8e000 | 0xb4000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 0 | @ 0x18000 | 0xae000000 | 0xbfc00 | 0x8e000000 | 0xbfc01 | 0x8e000000 | 0xbfc02 | 0xae000000 | 0xbfc03 | 0xae400000 | 0xbfc04 | 0x8e000000 | 0xbfc05 | 0 | 0 | 0 | 0
0 | way 1 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 0 | @ 0x13000 | 0xc0000019 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 0 | @ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_IDLE> Read request: srcid = 1 / address = 0x19480 / pktid = 0x1 / nwords = 16
****************** cycle 1701211 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_TLB_PTE1_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_DIR_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2.DCACHE_TLB_PTE1_GET> HIT in dcache / paddr = 0x000013000 / way = 2 / set = 0 / word = 0 / PTD = 0xc0000019
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
****************** cycle 1701212 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_DIR_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_TLB_PTE2_GET> MISS in dcache: PTE address = 0x000019480
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0 / rpktid = 3 / rdata = 0x27bdff98 / cpt = 0
****************** cycle 1701213 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_SELECT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_DIR_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_SELECT> Select a slot: / WAY = 0 / SET = 18 / PADDR = 0x000019480
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_LOCK> Accessing directory:  address = 0x19480 / hit = 1 / count = 2 / is_cnt = 0
  <MEMC memc_0_0.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0 / rpktid = 3 / rdata = 0xafbf0064 / cpt = 1
****************** cycle 1701214 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_DATA_MISS | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_HEAP_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x27bdff98 WAY = 0x1 SET = 0 WORD = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_REQ> Requesting HEAP lock 
****************** cycle 1701215 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_DATA_MISS | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_HEAP_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xafbf0064 WAY = 0x1 SET = 0 WORD = 0x1
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d2 / for address 0x000019480
  <MEMC memc_0_0.READ_HEAP_LOCK> Update directory: tag = 0x6 set = 82 way = 0 count = 3 is_cnt = 0
  <MEMC memc_0_0.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0 / rpktid = 3 / rdata = 0xafbe0060 / cpt = 2
****************** cycle 1701216 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_DATA_MISS | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_READ | TGT_RSP_XRAM | READ_HEAP_WRITE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xafbe0060 WAY = 0x1 SET = 0 WORD = 0x2
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_READ> Push into read_fifo: address = 0x000019480 srcid = 0d2 trdid = 0d0 pktid = 0d1 plen = 0d64
  <MEMC memc_0_0.READ_HEAP_WRITE> Add an entry in the heap: owner_id = 1 owner_ins = 0
  <MEMC memc_0_0.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0 / rpktid = 3 / rdata = 0x3a0f021 / cpt = 3
****************** cycle 1701217 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x3a0f021 WAY = 0x1 SET = 0 WORD = 0x3
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0 / rpktid = 3 / rdata = 0xc0001c3 / cpt = 4
****************** cycle 1701218 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xc0001c3 WAY = 0x1 SET = 0 WORD = 0x4
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0 / rpktid = 3 / rdata = 0 / cpt = 5
****************** cycle 1701219 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0 WAY = 0x1 SET = 0 WORD = 0x5
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0 / rpktid = 3 / rdata = 0xafc2005c / cpt = 6
****************** cycle 1701220 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xafc2005c WAY = 0x1 SET = 0 WORD = 0x6
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0 / rpktid = 3 / rdata = 0x8fc2005c / cpt = 7
****************** cycle 1701221 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x8fc2005c WAY = 0x1 SET = 0 WORD = 0x7
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0 / rpktid = 3 / rdata = 0x21082 / cpt = 8
****************** cycle 1701222 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x21082 WAY = 0x1 SET = 0 WORD = 0x8
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0 / rpktid = 3 / rdata = 0xafc20058 / cpt = 9
****************** cycle 1701223 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xafc20058 WAY = 0x1 SET = 0 WORD = 0x9
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0 / rpktid = 3 / rdata = 0x8fc2005c / cpt = 10
****************** cycle 1701224 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x8fc2005c WAY = 0x1 SET = 0 WORD = 0xa
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0 / rpktid = 3 / rdata = 0x30420003 / cpt = 11
****************** cycle 1701225 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x30420003 WAY = 0x1 SET = 0 WORD = 0xb
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0 / rpktid = 3 / rdata = 0xc0004f1 / cpt = 12
****************** cycle 1701226 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xc0004f1 WAY = 0x1 SET = 0 WORD = 0xc
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0 / rpktid = 3 / rdata = 0xafc20054 / cpt = 13
****************** cycle 1701227 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xafc20054 WAY = 0x1 SET = 0 WORD = 0xd
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0 / rpktid = 3 / rdata = 0xc000342 / cpt = 14
****************** cycle 1701228 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xc000342 WAY = 0x1 SET = 0 WORD = 0xe
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0 / rpktid = 3 / rdata = 0xafc20050 / cpt = 15
****************** cycle 1701229 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xafc20050 WAY = 0x1 SET = 0 WORD = 0xf
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701230 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 ICACHE_MISS_DIR_UPDT> Switch cache slot to VALID state PADDR = 0x00000d000 WAY = 1 SET = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701231 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701232 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0xaa000000 / cpt = 0
****************** cycle 1701233 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0xd / cpt = 1
****************** cycle 1701234 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0.DCACHE_TLB_MISS> DTLB miss / VADDR = 0xbfc0affc / BYPASS = 0 / PTE_ADR = 0x0000137f8
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xaa000000 / WAY = 0 / SET = 18 / WORD = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701235 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0.DCACHE_TLB_PTE1_GET> HIT in dcache / paddr = 0x0000137f8 / way = 3 / set = 31 / word = 14 / PTD = 0xc0000018
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xd / WAY = 0 / SET = 18 / WORD = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 2
****************** cycle 1701236 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_TLB_PTE2_GET> MISS in dcache: PTE address = 0x000018050
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 2
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 3
****************** cycle 1701237 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_MISS_SELECT> Select a slot: / WAY = 2 / SET = 1 / PADDR = 0x000018050 / VICTIM = 0x002ff0381
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 3
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 4
****************** cycle 1701238 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_MISS_CLEAN> Switch to ZOMBI state / way = 2 / set = 1
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 4
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 5
****************** cycle 1701239 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_dcache_cc_send_nline = 0x002ff0381
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d0 / for address 0x000018040
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 6
****************** cycle 1701240 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_READ | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_dcache_cc_send_nline = 0x002ff0381
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 6
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_READ> Push into read_fifo: address = 0x000018040 srcid = 0d0 trdid = 0d0 pktid = 0d1 plen = 0d64
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 7
****************** cycle 1701241 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 7
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 8
****************** cycle 1701242 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_CLEANUP | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 8
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 9
****************** cycle 1701243 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_CLEANUP | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 9
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CLEANUP_IDLE> Cleanup request: / owner_id = 0 / owner_ins = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 10
****************** cycle 1701244 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_GET_NLINE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 10
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CLEANUP_GET_NLINE> Cleanup request: / address = 0xbfc0e040
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 11
****************** cycle 1701245 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 11
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 12
****************** cycle 1701246 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 12
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CLEANUP_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 13
****************** cycle 1701247 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_DIR_LOCK
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 13
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CLEANUP_DIR_LOCK> Test directory status:  line = 0x000bfc0e040 / hit = 0 / dir_id = 0 / dir_ins = 0 / search_id = 0 / search_ins = 0 / count = 0 / is_cnt = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 14
****************** cycle 1701248 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_UPT_LOCK
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 14
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 15
****************** cycle 1701249 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_UPT_LOCK
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 15
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_RSP> Request the TGT_RSP FSM to return data: rsrcid = 1 / address = 0x19480 / nwords = 16
  <MEMC memc_0_0.CLEANUP_UPT_LOCK> Unexpected cleanup with no corresponding UPT entry: address = 0xbfc0e040
****************** cycle 1701250 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_SEND_ACK
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DIR_UPDT> Switch slot to VALID state PADDR = 0x000019480 / WAY = 0 / SET = 18
1 | way 0 | set 0 | @ 0xbfc0c000 | 0xbabef00d | 0x1 | 0x1 | 0x1 | 0xf | 0x4 | 0 | 0 | 0 | 0 | 0xb | 0x24 | 0x25 | 0x7 | 0x4 | 0x1c
0 | way 0 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 18 | @ 0x19480 | 0xaa000000 | 0xd | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 31 | @ 0x137c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xc0000018 | 0xc000001a
0 | way 0 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 62 | @ 0xbfc04f80 | 0x3000 | 0x12000 | 0x68000 | 0x8e000 | 0xb4000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 0 | @ 0x18000 | 0xae000000 | 0xbfc00 | 0x8e000000 | 0xbfc01 | 0x8e000000 | 0xbfc02 | 0xae000000 | 0xbfc03 | 0xae400000 | 0xbfc04 | 0x8e000000 | 0xbfc05 | 0 | 0 | 0 | 0
0 | way 1 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 0 | @ 0x13000 | 0xc0000019 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 0 | @ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_IDLE> Read request: srcid = 2 / address = 0x19480 / pktid = 0x1 / nwords = 16
  <MEMC memc_0_0.CLEANUP_SEND_ACK> Send the response to a cleanup request: srcid = 0
****************** cycle 1701251 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0xaa000000 PTE_PPN = 0xd
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
****************** cycle 1701252 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_ACK | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 1 / set = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.CC_SEND_CLEANUP_ACK> Cleanup Acknowledgement for srcid 0
****************** cycle 1701253 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB / set = 0 / way = 1
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
     [0] [0]   [1][1][0][1][1][1][0][0][0][0][1][0x17f80][  0xbfc00][0x000000600]
     [0] [1]   [1][1][0][1][0][1][0][0][0][0][1][0x10012][      0xd][0x000000652]
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_LOCK> Accessing directory:  address = 0x19480 / hit = 1 / count = 3 / is_cnt = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0xaa000000 / cpt = 0
****************** cycle 1701254 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_REQ> Requesting HEAP lock 
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0xd / cpt = 1
****************** cycle 1701255 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xaa000000 / WAY = 0 / SET = 18 / WORD = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_LOCK> Update directory: tag = 0x6 set = 82 way = 0 count = 4 is_cnt = 1
****************** cycle 1701256 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_ERASE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xd / WAY = 0 / SET = 18 / WORD = 1
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 2
****************** cycle 1701257 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_LAST | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_CC_CHECK> paddr = 0x000019480 r_dcache_vci_paddr = 0x000018050 mask = 0x0ffffffc0 (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) = 0x1 (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT) = 0 ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) = 0
  <PROC proc_0_0_0 DCACHE_CC_CHECK> CC_TYPE_CLACK Switch slot to EMPTY state set = 0x1 / way = 0x2
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 2
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 ICACHE_MISS_SELECT> Select a slot: / WAY = 1 / SET = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 3
****************** cycle 1701258 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 3
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 4
****************** cycle 1701259 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 4
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x00000d000
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 5
****************** cycle 1701260 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_READ | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 5
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_READ> Push into read_fifo: address = 0x00000d000 srcid = 0d3 trdid = 0d0 pktid = 0d3 plen = 0d64
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 6
****************** cycle 1701261 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 6
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 7
****************** cycle 1701262 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 7
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 8
****************** cycle 1701263 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 8
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 9
****************** cycle 1701264 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 9
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 10
****************** cycle 1701265 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 10
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 11
****************** cycle 1701266 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 11
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 12
****************** cycle 1701267 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 12
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 13
****************** cycle 1701268 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 13
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 14
****************** cycle 1701269 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 14
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 15
****************** cycle 1701270 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 15
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_RSP> Request the TGT_RSP FSM to return data: rsrcid = 2 / address = 0x19480 / nwords = 16
****************** cycle 1701271 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DIR_UPDT> Switch slot to VALID state PADDR = 0x000019480 / WAY = 0 / SET = 18
1 | way 0 | set 0 | @ 0xbfc0c000 | 0xbabef00d | 0x1 | 0x1 | 0x1 | 0xf | 0x4 | 0 | 0 | 0 | 0 | 0xb | 0x24 | 0x25 | 0x7 | 0x4 | 0x1c
0 | way 0 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 18 | @ 0x19480 | 0xaa000000 | 0xd | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 31 | @ 0x137c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xc0000018 | 0xc000001a
0 | way 0 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 61 | @ 0xbfc04f40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x1000 | 0x2000
1 | way 0 | set 62 | @ 0xbfc04f80 | 0x3000 | 0x12000 | 0x68000 | 0x8e000 | 0xb4000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 0 | @ 0x18000 | 0xae000000 | 0xbfc00 | 0x8e000000 | 0xbfc01 | 0x8e000000 | 0xbfc02 | 0xae000000 | 0xbfc03 | 0xae400000 | 0xbfc04 | 0x8e000000 | 0xbfc05 | 0 | 0 | 0 | 0
0 | way 1 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 0 | @ 0x13000 | 0xc0000019 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 0 | @ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_IDLE> Read request: srcid = 0 / address = 0x18040 / pktid = 0x1 / nwords = 16
****************** cycle 1701272 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0xaa000000 PTE_PPN = 0xd
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
****************** cycle 1701273 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 1 / set = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_LOCK> Accessing directory:  address = 0x18040 / hit = 1 / count = 0 / is_cnt = 0
****************** cycle 1701274 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_HIT | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB / set = 0 / way = 1
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
     [0] [0]   [1][1][0][1][1][1][0][0][0][0][1][0x17f80][  0xbfc00][0x000000600]
     [0] [1]   [1][1][0][1][0][1][0][0][0][0][1][0x10012][      0xd][0x000000652]
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_HIT> Update directory entry: addr = 0x18040 / set = 1 / way = 0 / owner_id = 0 / owner_ins = 0 / count = 1 / is_cnt = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0xaa000000 / cpt = 0
****************** cycle 1701275 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_WAIT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0xd / cpt = 1
****************** cycle 1701276 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xaa000000 / WAY = 0 / SET = 18 / WORD = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701277 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xd / WAY = 0 / SET = 18 / WORD = 1
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 2
****************** cycle 1701278 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 ICACHE_MISS_SELECT> Select a slot: / WAY = 1 / SET = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 2
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 3
****************** cycle 1701279 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 3
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 4
****************** cycle 1701280 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 4
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d1 / for address 0x00000d000
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 5
****************** cycle 1701281 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_READ | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 5
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_READ> Push into read_fifo: address = 0x00000d000 srcid = 0d1 trdid = 0d0 pktid = 0d3 plen = 0d64
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 6
****************** cycle 1701282 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 6
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 7
****************** cycle 1701283 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 7
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 8
****************** cycle 1701284 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 8
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 9
****************** cycle 1701285 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 9
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 10
****************** cycle 1701286 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 10
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 11
****************** cycle 1701287 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 11
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 12
****************** cycle 1701288 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 12
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 13
****************** cycle 1701289 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 13
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 14
****************** cycle 1701290 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 14
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 15
****************** cycle 1701291 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 18 / WORD = 15
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_RSP> Request the TGT_RSP FSM to return data: rsrcid = 0 / address = 0x18040 / nwords = 16
****************** cycle 1701292 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_MISS_DIR_UPDT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DIR_UPDT> Switch slot to VALID state PADDR = 0x000019480 / WAY = 0 / SET = 18
1 | way 0 | set 0 | @ 0xbfc0c000 | 0xbabef00d | 0x1 | 0x1 | 0x1 | 0xf | 0x4 | 0 | 0 | 0 | 0 | 0xb | 0x24 | 0x25 | 0x7 | 0x4 | 0x1c
0 | way 0 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 18 | @ 0x19480 | 0xaa000000 | 0xd | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 31 | @ 0x137c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xc0000018 | 0xc000001a
0 | way 0 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 61 | @ 0xbfc04f40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x1000 | 0x2000
1 | way 0 | set 62 | @ 0xbfc04f80 | 0x3000 | 0x12000 | 0x68000 | 0x8e000 | 0xb4000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 0 | @ 0x18000 | 0xae000000 | 0xbfc00 | 0x8e000000 | 0xbfc01 | 0x8e000000 | 0xbfc02 | 0xae000000 | 0xbfc03 | 0xae400000 | 0xbfc04 | 0x8e000000 | 0xbfc05 | 0 | 0 | 0 | 0
0 | way 1 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 0 | @ 0x13000 | 0xc0000019 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 0 | @ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_IDLE> Read request: srcid = 3 / address = 0xd000 / pktid = 0x3 / nwords = 16
****************** cycle 1701293 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0xaa000000 PTE_PPN = 0xd
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
****************** cycle 1701294 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_TLB_PTE2_SELECT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 1 / set = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_LOCK> Accessing directory:  address = 0xd000 / hit = 1 / count = 1 / is_cnt = 0
****************** cycle 1701295 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_TLB_PTE2_UPDT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB / set = 0 / way = 1
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
     [0] [0]   [1][1][0][1][1][1][0][0][0][0][1][0x17f80][  0xbfc00][0x000000600]
     [0] [1]   [1][1][0][1][0][1][0][0][0][0][1][0x10012][      0xd][0x000000652]
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_REQ> Requesting HEAP lock 
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0x8c000000 / cpt = 0
****************** cycle 1701296 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_TLB_RETURN | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_LOCK> Update directory: tag = 0x3 set = 64 way = 7 count = 2 is_cnt = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc08 / cpt = 1
****************** cycle 1701297 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_TLB_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_WRITE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x8c000000 / WAY = 2 / SET = 1 / WORD = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_WRITE> Add an entry in the heap: owner_id = 3 owner_ins = 1
****************** cycle 1701298 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc08 / WAY = 2 / SET = 1 / WORD = 1
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0x8c000000 / cpt = 2
****************** cycle 1701299 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_SELECT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x8c000000 / WAY = 2 / SET = 1 / WORD = 2
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 ICACHE_MISS_SELECT> Select a slot: / WAY = 1 / SET = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc09 / cpt = 3
****************** cycle 1701300 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc09 / WAY = 2 / SET = 1 / WORD = 3
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0xac400000 / cpt = 4
****************** cycle 1701301 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xac400000 / WAY = 2 / SET = 1 / WORD = 4
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d2 / for address 0x00000d000
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc0a / cpt = 5
****************** cycle 1701302 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_READ | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc0a / WAY = 2 / SET = 1 / WORD = 5
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_READ> Push into read_fifo: address = 0x00000d000 srcid = 0d2 trdid = 0d0 pktid = 0d3 plen = 0d64
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0x8c000000 / cpt = 6
****************** cycle 1701303 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x8c000000 / WAY = 2 / SET = 1 / WORD = 6
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc0b / cpt = 7
****************** cycle 1701304 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc0b / WAY = 2 / SET = 1 / WORD = 7
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0xac000000 / cpt = 8
****************** cycle 1701305 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xac000000 / WAY = 2 / SET = 1 / WORD = 8
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc0c / cpt = 9
****************** cycle 1701306 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc0c / WAY = 2 / SET = 1 / WORD = 9
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0xac000000 / cpt = 10
****************** cycle 1701307 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xac000000 / WAY = 2 / SET = 1 / WORD = 10
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc0d / cpt = 11
****************** cycle 1701308 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc0d / WAY = 2 / SET = 1 / WORD = 11
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0xac000000 / cpt = 12
****************** cycle 1701309 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xac000000 / WAY = 2 / SET = 1 / WORD = 12
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc0e / cpt = 13
****************** cycle 1701310 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc0e / WAY = 2 / SET = 1 / WORD = 13
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 14
****************** cycle 1701311 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 1 / WORD = 14
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 15
****************** cycle 1701312 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 1 / WORD = 15
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_RSP> Request the TGT_RSP FSM to return data: rsrcid = 3 / address = 0xd000 / nwords = 16
****************** cycle 1701313 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DIR_UPDT> Switch slot to VALID state PADDR = 0x000018050 / WAY = 2 / SET = 1
1 | way 0 | set 0 | @ 0x13000 | 0xc0000019 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 1 | @ 0x94040 | 0x8c000000 | 0xbfc08 | 0x8c000000 | 0xbfc09 | 0xac400000 | 0xbfc0a | 0x8c000000 | 0xbfc0b | 0xac000000 | 0xbfc0c | 0xac000000 | 0xbfc0d | 0x8c000000 | 0xbfc0e | 0 | 0
1 | way 0 | set 2 | @ 0xbfc0c080 | 0 | 0x6 | 0 | 0x47455350 | 0x4d41525f | 0 | 0 | 0 | 0 | 0 | 0x75000000 | 0 | 0xc00000 | 0 | 0 | 0xd6000
1 | way 0 | set 3 | @ 0xbfc0e0c0 | 0x12 | 0x2 | 0x2 | 0 | 0x13 | 0x2 | 0x3 | 0 | 0x14 | 0x2 | 0x4 | 0 | 0x15 | 0x2 | 0x5 | 0
1 | way 0 | set 4 | @ 0xbfc0e100 | 0x16 | 0x2 | 0x6 | 0 | 0x17 | 0x2 | 0x7 | 0 | 0x18 | 0x2 | 0x8 | 0 | 0x19 | 0x2 | 0x9 | 0
1 | way 0 | set 5 | @ 0xbfc0c140 | 0 | 0 | 0xf00000 | 0x1000 | 0x2 | 0 | 0xf00000 | 0x47455350 | 0x434f495f | 0 | 0 | 0 | 0 | 0 | 0 | 0xbff10000
1 | way 0 | set 6 | @ 0xbfc0e180 | 0x1e | 0x2 | 0xe | 0 | 0x1f | 0x4 | 0 | 0x1 | 0x1 | 0x1 | 0 | 0x1 | 0x2 | 0x1 | 0 | 0x1
1 | way 0 | set 7 | @ 0xbc1c0 | 0x84000000 | 0xbfe38 | 0x84000000 | 0xbfe39 | 0x84000000 | 0xbfe3a | 0x84000000 | 0xbfe3b | 0x84000000 | 0xbfe3c | 0x84000000 | 0xbfe3d | 0x84000000 | 0xbfe3e | 0x84000000 | 0xbfe3f
1 | way 0 | set 8 | @ 0xbfc0c200 | 0 | 0 | 0 | 0 | 0 | 0 | 0xbff80000 | 0x21000 | 0x2 | 0 | 0xbff80000 | 0x47455350 | 0x4443475f | 0 | 0 | 0
1 | way 0 | set 9 | @ 0x6e240 | 0x84000000 | 0xbfe48 | 0x84000000 | 0xbfe49 | 0x84000000 | 0xbfe4a | 0x84000000 | 0xbfe4b | 0x84000000 | 0xbfe4c | 0x84000000 | 0xbfe4d | 0x84000000 | 0xbfe4e | 0x84000000 | 0xbfe4f
1 | way 0 | set 10 | @ 0x6e280 | 0x84000000 | 0xbfe50 | 0x84000000 | 0xbfe51 | 0x84000000 | 0xbfe52 | 0x84000000 | 0xbfe53 | 0x84000000 | 0xbfe54 | 0x84000000 | 0xbfe55 | 0x84000000 | 0xbfe56 | 0x84000000 | 0xbfe57
1 | way 0 | set 11 | @ 0x962c0 | 0x84000000 | 0xbfe58 | 0x84000000 | 0xbfe59 | 0x84000000 | 0xbfe5a | 0x84000000 | 0xbfe5b | 0x84000000 | 0xbfe5c | 0x84000000 | 0xbfe5d | 0x84000000 | 0xbfe5e | 0x84000000 | 0xbfe5f
1 | way 0 | set 12 | @ 0x96300 | 0x84000000 | 0xbfe60 | 0x84000000 | 0xbfe61 | 0x84000000 | 0xbfe62 | 0x84000000 | 0xbfe63 | 0x84000000 | 0xbfe64 | 0x84000000 | 0xbfe65 | 0x84000000 | 0xbfe66 | 0x84000000 | 0xbfe67
1 | way 0 | set 13 | @ 0xbc340 | 0x84000000 | 0xbfe68 | 0x84000000 | 0xbfe69 | 0x84000000 | 0xbfe6a | 0x84000000 | 0xbfe6b | 0x84000000 | 0xbfe6c | 0x84000000 | 0xbfe6d | 0x84000000 | 0xbfe6e | 0x84000000 | 0xbfe6f
1 | way 0 | set 14 | @ 0x96380 | 0x84000000 | 0xbfe70 | 0x84000000 | 0xbfe71 | 0x84000000 | 0xbfe72 | 0x84000000 | 0xbfe73 | 0x84000000 | 0xbfe74 | 0x84000000 | 0xbfe75 | 0x84000000 | 0xbfe76 | 0x84000000 | 0xbfe77
1 | way 0 | set 15 | @ 0xbfc043c0 | 0xff0106d | 0 | 0x3c0e821 | 0x8fbf0014 | 0x8fbe0010 | 0x27bd0018 | 0x3e00008 | 0 | 0x33323130 | 0x37363534 | 0x42413938 | 0x46454443 | 0 | 0x33323130 | 0x37363534 | 0x3938
1 | way 0 | set 16 | @ 0xbfc0d400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x2fc | 0 | 0x800000 | 0xe000 | 0 | 0x65646f63 | 0
1 | way 0 | set 17 | @ 0xbfc04440 | 0x6974636e | 0x62206e6f | 0x5f746f6f | 0x67657370 | 0x7465675f | 0xa2928 | 0x6f666e55 | 0x20646e75 | 0x65676170 | 0x62617420 | 0x6620656c | 0x7620726f | 0x63617073 | 0x2065 | 0xa | 0x4f425b0a
1 | way 0 | set 18 | @ 0xbfc0d480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x240c | 0 | 0x400000 | 0xf000 | 0 | 0x62617470 | 0 | 0 | 0
1 | way 0 | set 19 | @ 0xbfc0c4c0 | 0x645f6c65 | 0x617461 | 0 | 0 | 0 | 0 | 0x80010000 | 0x8000 | 0x4000 | 0 | 0xa | 0 | 0x1 | 0x4 | 0x5f676573 | 0x6e72656b
1 | way 0 | set 20 | @ 0xbfc0d500 | 0 | 0 | 0 | 0 | 0x2 | 0x12000 | 0xd | 0x300000 | 0x12000 | 0 | 0x63617473 | 0x705f6b | 0 | 0 | 0 | 0
1 | way 0 | set 21 | @ 0xbfc0c540 | 0x695f6c65 | 0x74696e | 0 | 0 | 0 | 0 | 0x80090000 | 0xd000 | 0x1000 | 0 | 0xc | 0 | 0x1 | 0x6 | 0x5f676573 | 0x666266
1 | way 0 | set 22 | @ 0xbfc0d580 | 0 | 0 | 0x6 | 0x10000 | 0 | 0x10000 | 0x24000 | 0 | 0x63617473 | 0x635f6b | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 23 | @ 0xbfc0c5c0 | 0 | 0 | 0 | 0 | 0 | 0x20000000 | 0xf00000 | 0xf00000 | 0x1000 | 0x3 | 0x2 | 0x1 | 0x1 | 0x8 | 0x5f676573 | 0x636f69
1 | way 0 | set 24 | @ 0xbfc0c600 | 0 | 0 | 0 | 0 | 0 | 0 | 0xbff10000 | 0xbff10000 | 0x1000 | 0x4 | 0x2 | 0x1 | 0x1 | 0x9 | 0x5f676573 | 0x797474
1 | way 0 | set 25 | @ 0xbfc0c640 | 0 | 0 | 0 | 0 | 0 | 0 | 0xbff20000 | 0xbff20000 | 0x1000 | 0x5 | 0x2 | 0x1 | 0x1 | 0xa | 0x5f676573 | 0x616d64
1 | way 0 | set 26 | @ 0xbfc0c680 | 0 | 0 | 0 | 0 | 0 | 0 | 0xf30000 | 0xf30000 | 0x1000 | 0x6 | 0x2 | 0x1 | 0x1 | 0xb | 0x5f676573 | 0x646367
1 | way 0 | set 27 | @ 0xbfc0c6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xf50000 | 0xf50000 | 0x1000 | 0x8 | 0x2 | 0x1 | 0x1 | 0xc | 0x5f676573 | 0x626f69
1 | way 0 | set 28 | @ 0xbfc0c700 | 0 | 0 | 0 | 0 | 0 | 0 | 0xff0000 | 0xff0000 | 0x1000 | 0xa | 0x2 | 0x1 | 0x1 | 0xd | 0x5f676573 | 0x63696e
1 | way 0 | set 29 | @ 0xbfc0c740 | 0 | 0 | 0 | 0 | 0 | 0 | 0xbffa0000 | 0xbffa0000 | 0x1000 | 0x7 | 0x2 | 0x1 | 0x1 | 0xe | 0x5f676573 | 0x61746164
1 | way 0 | set 30 | @ 0xbc780 | 0x84000000 | 0xbfef0 | 0x84000000 | 0xbfef1 | 0x84000000 | 0xbfef2 | 0x84000000 | 0xbfef3 | 0x84000000 | 0xbfef4 | 0x84000000 | 0xbfef5 | 0x84000000 | 0xbfef6 | 0x84000000 | 0xbfef7
1 | way 0 | set 31 | @ 0x697c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xc000006f | 0xc000006e
1 | way 0 | set 32 | @ 0xb8800 | 0x88000000 | 0xb4 | 0x88000000 | 0xb5 | 0x88000000 | 0xb6 | 0x88000000 | 0xb7 | 0x88000000 | 0xb8 | 0x88000000 | 0xb9 | 0x88000000 | 0xba | 0x88000000 | 0xbb
1 | way 0 | set 33 | @ 0xbfc0d840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x94 | 0 | 0x800000 | 0x65000 | 0 | 0x65646f63 | 0 | 0 | 0
1 | way 0 | set 34 | @ 0xb8880 | 0x88000000 | 0xc4 | 0x88000000 | 0xc5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 35 | @ 0x948c0 | 0x84000000 | 0xbfd18 | 0x84000000 | 0xbfd19 | 0x84000000 | 0xbfd1a | 0x84000000 | 0xbfd1b | 0x84000000 | 0xbfd1c | 0x84000000 | 0xbfd1d | 0x84000000 | 0xbfd1e | 0x84000000 | 0xbfd1f
1 | way 0 | set 36 | @ 0xba900 | 0x84000000 | 0xbfd20 | 0x84000000 | 0xbfd21 | 0x84000000 | 0xbfd22 | 0x84000000 | 0xbfd23 | 0x84000000 | 0xbfd24 | 0x84000000 | 0xbfd25 | 0x84000000 | 0xbfd26 | 0x84000000 | 0xbfd27
1 | way 0 | set 37 | @ 0xbfc0d940 | 0 | 0 | 0x2 | 0x12000 | 0xd | 0x300000 | 0x68000 | 0 | 0x63617473 | 0x6b | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 38 | @ 0xba980 | 0x84000000 | 0xbfd30 | 0x84000000 | 0xbfd31 | 0x84000000 | 0xbfd32 | 0x84000000 | 0xbfd33 | 0x84000000 | 0xbfd34 | 0x84000000 | 0xbfd35 | 0x84000000 | 0xbfd36 | 0x84000000 | 0xbfd37
1 | way 0 | set 39 | @ 0x949c0 | 0x84000000 | 0xbfd38 | 0x84000000 | 0xbfd39 | 0x84000000 | 0xbfd3a | 0x84000000 | 0xbfd3b | 0x84000000 | 0xbfd3c | 0x84000000 | 0xbfd3d | 0x84000000 | 0xbfd3e | 0x84000000 | 0xbfd3f
1 | way 0 | set 40 | @ 0x94a00 | 0x84000000 | 0xbfd40 | 0x84000000 | 0xbfd41 | 0x84000000 | 0xbfd42 | 0x84000000 | 0xbfd43 | 0x84000000 | 0xbfd44 | 0x84000000 | 0xbfd45 | 0x84000000 | 0xbfd46 | 0x84000000 | 0xbfd47
1 | way 0 | set 41 | @ 0x94a40 | 0x84000000 | 0xbfd48 | 0x84000000 | 0xbfd49 | 0x84000000 | 0xbfd4a | 0x84000000 | 0xbfd4b | 0x84000000 | 0xbfd4c | 0x84000000 | 0xbfd4d | 0x84000000 | 0xbfd4e | 0x84000000 | 0xbfd4f
1 | way 0 | set 42 | @ 0xbda80 | 0x84000000 | 0xf50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 43 | @ 0xbaac0 | 0x84000000 | 0xbfd58 | 0x84000000 | 0xbfd59 | 0x84000000 | 0xbfd5a | 0x84000000 | 0xbfd5b | 0x84000000 | 0xbfd5c | 0x84000000 | 0xbfd5d | 0x84000000 | 0xbfd5e | 0x84000000 | 0xbfd5f
1 | way 0 | set 44 | @ 0xbab00 | 0x84000000 | 0xbfd60 | 0x84000000 | 0xbfd61 | 0x84000000 | 0xbfd62 | 0x84000000 | 0xbfd63 | 0x84000000 | 0xbfd64 | 0x84000000 | 0xbfd65 | 0x84000000 | 0xbfd66 | 0x84000000 | 0xbfd67
1 | way 0 | set 45 | @ 0xbfc04b40 | 0x7461636f | 0x2073726f | 0x74696e69 | 0x696c6169 | 0x69746173 | 0x63206e6f | 0x6c706d6f | 0x64657465 | 0x20746120 | 0x6c637963 | 0x2065 | 0x4f425b0a | 0x205d544f | 0x65676150 | 0x62615420 | 0x2073656c
1 | way 0 | set 46 | @ 0xbfc04b80 | 0x74696e69 | 0x696c6169 | 0x69746173 | 0x63206e6f | 0x6c706d6f | 0x64657465 | 0x20746120 | 0x6c637963 | 0x2065 | 0x4f425b0a | 0x205d544f | 0x6a626f56 | 0x6e692073 | 0x61697469 | 0x6173696c | 0x6e6f6974
1 | way 0 | set 47 | @ 0xbfc0cbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x800000 | 0xb0000 | 0x1000 | 0 | 0xb | 0 | 0x1 | 0x21 | 0x5f676573 | 0x65646f63
1 | way 0 | set 48 | @ 0xbfc0dc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0x6 | 0x10000 | 0 | 0x10000 | 0xa0000 | 0 | 0x61746164 | 0 | 0 | 0
1 | way 0 | set 49 | @ 0xbfc0cc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0x300000 | 0xb4000 | 0x12000 | 0 | 0x8 | 0 | 0x1 | 0x23 | 0x5f676573 | 0x63617473
1 | way 0 | set 50 | @ 0xbac80 | 0x84000000 | 0xbfd90 | 0x84000000 | 0xbfd91 | 0x84000000 | 0xbfd92 | 0x84000000 | 0xbfd93 | 0x84000000 | 0xbfd94 | 0x84000000 | 0xbfd95 | 0x84000000 | 0xbfd96 | 0x84000000 | 0xbfd97
1 | way 0 | set 51 | @ 0x18cc0 | 0x84000000 | 0xbfd98 | 0x84000000 | 0xbfd99 | 0x84000000 | 0xbfd9a | 0x84000000 | 0xbfd9b | 0x84000000 | 0xbfd9c | 0x84000000 | 0xbfd9d | 0x84000000 | 0xbfd9e | 0x84000000 | 0xbfd9f
1 | way 0 | set 52 | @ 0xbfc0dd00 | 0 | 0 | 0 | 0x1714 | 0 | 0x400000 | 0xb1000 | 0 | 0x62617470 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 53 | @ 0xbfc04d40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x10 | 0x10 | 0x10
1 | way 0 | set 54 | @ 0xbfc0dd80 | 0x2 | 0x12000 | 0xd | 0x300000 | 0xb4000 | 0 | 0x63617473 | 0x6b | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 55 | @ 0xbadc0 | 0x84000000 | 0xbfdb8 | 0x84000000 | 0xbfdb9 | 0x84000000 | 0xbfdba | 0x84000000 | 0xbfdbb | 0x84000000 | 0xbfdbc | 0x84000000 | 0xbfdbd | 0x84000000 | 0xbfdbe | 0x84000000 | 0xbfdbf
1 | way 0 | set 56 | @ 0x94e00 | 0x84000000 | 0xbfdc0 | 0x84000000 | 0xbfdc1 | 0x84000000 | 0xbfdc2 | 0x84000000 | 0xbfdc3 | 0x84000000 | 0xbfdc4 | 0x84000000 | 0xbfdc5 | 0x84000000 | 0xbfdc6 | 0x84000000 | 0xbfdc7
1 | way 0 | set 57 | @ 0xbfc04e40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x300000 | 0x300000 | 0x300000
1 | way 0 | set 58 | @ 0xbae80 | 0x84000000 | 0xbfdd0 | 0x84000000 | 0xbfdd1 | 0x84000000 | 0xbfdd2 | 0x84000000 | 0xbfdd3 | 0x84000000 | 0xbfdd4 | 0x84000000 | 0xbfdd5 | 0x84000000 | 0xbfdd6 | 0x84000000 | 0xbfdd7
1 | way 0 | set 59 | @ 0xbaec0 | 0x84000000 | 0xbfdd8 | 0x84000000 | 0xbfdd9 | 0x84000000 | 0xbfdda | 0x84000000 | 0xbfddb | 0x84000000 | 0xbfddc | 0x84000000 | 0xbfddd | 0x84000000 | 0xbfdde | 0x84000000 | 0xbfddf
1 | way 0 | set 60 | @ 0x3f00 | 0x2 | 0 | 0 | 0 | 0 | 0x101 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 61 | @ 0xbfc0af40 | 0x400000 | 0x800000 | 0xbfc0dc30 | 0 | 0xffffffff | 0xffffffff | 0x7 | 0x300000 | 0 | 0x5a | 0xff13 | 0xbfc0067c | 0x101 | 0 | 0x1 | 0x3
1 | way 0 | set 62 | @ 0xbfc0af80 | 0x1 | 0x20 | 0x4 | 0 | 0x1 | 0x7 | 0x4 | 0 | 0x7 | 0xbff20000 | 0x1 | 0xbfc0afb0 | 0xbfc0afcb | 0xbfc0e00c | 0xbfc0dfec | 0xbfc0ccb8
1 | way 0 | set 63 | @ 0xbfc0afc0 | 0x3 | 0x7 | 0x31c0c08c | 0x35373936 | 0xbf003136 | 0x1 | 0xbfc0c000 | 0xbff20000 | 0xbfc0afe8 | 0xbfc0afe8 | 0xbfc04478 | 0 | 0 | 0 | 0 | 0xbfc00524
1 | way 1 | set 0 | @ 0x18000 | 0xae000000 | 0xbfc00 | 0x8e000000 | 0xbfc01 | 0x8e000000 | 0xbfc02 | 0xae000000 | 0xbfc03 | 0xae400000 | 0xbfc04 | 0x8e000000 | 0xbfc05 | 0 | 0 | 0 | 0
1 | way 1 | set 1 | @ 0xba040 | 0x8c000000 | 0xbfc08 | 0x8c000000 | 0xbfc09 | 0xac400000 | 0xbfc0a | 0x8c000000 | 0xbfc0b | 0xac400000 | 0xbfc0c | 0xac000000 | 0xbfc0d | 0x8c000000 | 0xbfc0e | 0 | 0
1 | way 1 | set 2 | @ 0xbfc0e080 | 0xe | 0x3 | 0x6 | 0 | 0xf | 0x3 | 0x7 | 0 | 0x10 | 0x2 | 0 | 0 | 0x11 | 0x2 | 0x1 | 0
1 | way 1 | set 3 | @ 0xb90c0 | 0x8d000000 | 0xce | 0x8d000000 | 0xcf | 0x8d000000 | 0xd0 | 0x8d000000 | 0xd1 | 0x8d000000 | 0xd2 | 0x8d000000 | 0xd3 | 0x8d000000 | 0xd4 | 0x8d000000 | 0xd5
1 | way 1 | set 4 | @ 0xbc100 | 0x84000000 | 0xbfe20 | 0x84000000 | 0xbfe21 | 0x84000000 | 0xbfe22 | 0x84000000 | 0xbfe23 | 0x84000000 | 0xbfe24 | 0x84000000 | 0xbfe25 | 0x84000000 | 0xbfe26 | 0x84000000 | 0xbfe27
1 | way 1 | set 5 | @ 0xbfc0e140 | 0x1a | 0x2 | 0xa | 0 | 0x1b | 0x2 | 0xb | 0 | 0x1c | 0x2 | 0xc | 0 | 0x1d | 0x2 | 0xd | 0
1 | way 1 | set 6 | @ 0xbc180 | 0x84000000 | 0xbfe30 | 0x84000000 | 0xbfe31 | 0x84000000 | 0xbfe32 | 0x84000000 | 0xbfe33 | 0x84000000 | 0xbfe34 | 0x84000000 | 0xbfe35 | 0x84000000 | 0xbfe36 | 0x84000000 | 0xbfe37
1 | way 1 | set 7 | @ 0xbfc0e1c0 | 0x3 | 0x1 | 0 | 0x4 | 0x4 | 0x1 | 0x7 | 0x7 | 0x8 | 0x5 | 0x5 | 0x8 | 0x3 | 0x6 | 0x1 | 0x2
1 | way 1 | set 8 | @ 0xbfc0e200 | 0x3 | 0x5 | 0x6 | 0x2 | 0x1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 9 | @ 0x96240 | 0x84000000 | 0xbfe48 | 0x84000000 | 0xbfe49 | 0x84000000 | 0xbfe4a | 0x84000000 | 0xbfe4b | 0x84000000 | 0xbfe4c | 0x84000000 | 0xbfe4d | 0x84000000 | 0xbfe4e | 0x84000000 | 0xbfe4f
1 | way 1 | set 10 | @ 0x96280 | 0x84000000 | 0xbfe50 | 0x84000000 | 0xbfe51 | 0x84000000 | 0xbfe52 | 0x84000000 | 0xbfe53 | 0x84000000 | 0xbfe54 | 0x84000000 | 0xbfe55 | 0x84000000 | 0xbfe56 | 0x84000000 | 0xbfe57
1 | way 1 | set 11 | @ 0xbc2c0 | 0x84000000 | 0xbfe58 | 0x84000000 | 0xbfe59 | 0x84000000 | 0xbfe5a | 0x84000000 | 0xbfe5b | 0x84000000 | 0xbfe5c | 0x84000000 | 0xbfe5d | 0x84000000 | 0xbfe5e | 0x84000000 | 0xbfe5f
1 | way 1 | set 12 | @ 0xbc300 | 0x84000000 | 0xbfe60 | 0x84000000 | 0xbfe61 | 0x84000000 | 0xbfe62 | 0x84000000 | 0xbfe63 | 0x84000000 | 0xbfe64 | 0x84000000 | 0xbfe65 | 0x84000000 | 0xbfe66 | 0x84000000 | 0xbfe67
1 | way 1 | set 13 | @ 0xbfc0c340 | 0x64636770 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x4 | 0x4 | 0x1 | 0x1c | 0x1d | 0x5 | 0x70736964
1 | way 1 | set 14 | @ 0xbfc0c380 | 0x79616c | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x4 | 0x4 | 0x1 | 0x20 | 0x21 | 0x6 | 0x5f676573 | 0x746f6f62
1 | way 1 | set 15 | @ 0xbfc0c3c0 | 0x646f635f | 0x65 | 0 | 0 | 0 | 0 | 0xbfc00000 | 0xbfc00000 | 0x6000 | 0x1 | 0xe | 0x1 | 0x1 | 0 | 0x5f676573 | 0x746f6f62
1 | way 1 | set 16 | @ 0xbb400 | 0x84000000 | 0xc | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 17 | @ 0xbfc0c440 | 0x70616d5f | 0x676e6970 | 0 | 0 | 0 | 0 | 0xbfc0c000 | 0xbfc0c000 | 0x3000 | 0x1 | 0xa | 0x1 | 0x1 | 0x2 | 0x5f676573 | 0x6e72656b
1 | way 1 | set 18 | @ 0x19480 | 0xaa000000 | 0xd | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 19 | @ 0xbc4c0 | 0x84000000 | 0xbfe98 | 0x84000000 | 0xbfe99 | 0x84000000 | 0xbfe9a | 0x84000000 | 0xbfe9b | 0x84000000 | 0xbfe9c | 0x84000000 | 0xbfe9d | 0x84000000 | 0xbfe9e | 0x84000000 | 0xbfe9f
1 | way 1 | set 20 | @ 0x96500 | 0x84000000 | 0xbfea0 | 0x84000000 | 0xbfea1 | 0x84000000 | 0xbfea2 | 0x84000000 | 0xbfea3 | 0x84000000 | 0xbfea4 | 0x84000000 | 0xbfea5 | 0x84000000 | 0xbfea6 | 0x84000000 | 0xbfea7
1 | way 1 | set 21 | @ 0xbc540 | 0x84000000 | 0xbfea8 | 0x84000000 | 0xbfea9 | 0x84000000 | 0xbfeaa | 0x84000000 | 0xbfeab | 0x84000000 | 0xbfeac | 0x84000000 | 0xbfead | 0x84000000 | 0xbfeae | 0x84000000 | 0xbfeaf
1 | way 1 | set 22 | @ 0x96580 | 0x84000000 | 0xbfeb0 | 0x84000000 | 0xbfeb1 | 0x84000000 | 0xbfeb2 | 0x84000000 | 0xbfeb3 | 0x84000000 | 0xbfeb4 | 0x84000000 | 0xbfeb5 | 0x84000000 | 0xbfeb6 | 0x84000000 | 0xbfeb7
1 | way 1 | set 23 | @ 0xbc5c0 | 0x84000000 | 0xbfeb8 | 0x84000000 | 0xbfeb9 | 0x84000000 | 0xbfeba | 0x84000000 | 0xbfebb | 0x84000000 | 0xbfebc | 0x84000000 | 0xbfebd | 0x84000000 | 0xbfebe | 0x84000000 | 0xbfebf
1 | way 1 | set 24 | @ 0xbfc0d600 | 0x6 | 0x10000 | 0 | 0x20000 | 0x34000 | 0 | 0x63617473 | 0x41725f6b | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 25 | @ 0xbfc0d640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x6 | 0x10000
1 | way 1 | set 26 | @ 0xbfc0d680 | 0 | 0x30000 | 0x44000 | 0 | 0x63617473 | 0x42725f6b | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 27 | @ 0xbfc0d6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x6 | 0x10000 | 0 | 0x40000
1 | way 1 | set 28 | @ 0xbc700 | 0x84000000 | 0xbfee0 | 0x84000000 | 0xbfee1 | 0x84000000 | 0xbfee2 | 0x84000000 | 0xbfee3 | 0x84000000 | 0xbfee4 | 0x84000000 | 0xbfee5 | 0x84000000 | 0xbfee6 | 0x84000000 | 0xbfee7
1 | way 1 | set 29 | @ 0xbfc0d740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x4 | 0x20 | 0 | 0x50000 | 0x64000 | 0x1
1 | way 1 | set 30 | @ 0x1a780 | 0x84000000 | 0xbfef0 | 0x84000000 | 0xbfef1 | 0x84000000 | 0xbfef2 | 0x84000000 | 0xbfef3 | 0x84000000 | 0xbfef4 | 0x84000000 | 0xbfef5 | 0x84000000 | 0xbfef6 | 0x84000000 | 0xbfef7
1 | way 1 | set 31 | @ 0x8f7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xc0000094 | 0xc0000096
1 | way 1 | set 32 | @ 0xba800 | 0x84000000 | 0xbfd00 | 0x84000000 | 0xbfd01 | 0x84000000 | 0xbfd02 | 0x84000000 | 0xbfd03 | 0x84000000 | 0xbfd04 | 0x84000000 | 0xbfd05 | 0x84000000 | 0xbfd06 | 0x84000000 | 0xbfd07
1 | way 1 | set 33 | @ 0xb8840 | 0x88000000 | 0xbc | 0x88000000 | 0xbd | 0x88000000 | 0xbe | 0x88000000 | 0xbf | 0x88000000 | 0xc0 | 0x88000000 | 0xc1 | 0x88000000 | 0xc2 | 0x88000000 | 0xc3
1 | way 1 | set 34 | @ 0xba880 | 0x84000000 | 0xbfd10 | 0x84000000 | 0xbfd11 | 0x84000000 | 0xbfd12 | 0x84000000 | 0xbfd13 | 0x84000000 | 0xbfd14 | 0x84000000 | 0xbfd15 | 0x84000000 | 0xbfd16 | 0x84000000 | 0xbfd17
1 | way 1 | set 35 | @ 0xba8c0 | 0x84000000 | 0xbfd18 | 0x84000000 | 0xbfd19 | 0x84000000 | 0xbfd1a | 0x84000000 | 0xbfd1b | 0x84000000 | 0xbfd1c | 0x84000000 | 0xbfd1d | 0x84000000 | 0xbfd1e | 0x84000000 | 0xbfd1f
1 | way 1 | set 36 | @ 0xbc900 | 0xa4400000 | 0xbff20 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 37 | @ 0xba940 | 0x84000000 | 0xbfd28 | 0x84000000 | 0xbfd29 | 0x84000000 | 0xbfd2a | 0x84000000 | 0xbfd2b | 0x84000000 | 0xbfd2c | 0x84000000 | 0xbfd2d | 0x84000000 | 0xbfd2e | 0x84000000 | 0xbfd2f
1 | way 1 | set 38 | @ 0xbd980 | 0x84000000 | 0xf30 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 39 | @ 0xba9c0 | 0x84000000 | 0xbfd38 | 0x84000000 | 0xbfd39 | 0x84000000 | 0xbfd3a | 0x84000000 | 0xbfd3b | 0x84000000 | 0xbfd3c | 0x84000000 | 0xbfd3d | 0x84000000 | 0xbfd3e | 0x84000000 | 0xbfd3f
1 | way 1 | set 40 | @ 0xbaa00 | 0x84000000 | 0xbfd40 | 0x84000000 | 0xbfd41 | 0x84000000 | 0xbfd42 | 0x84000000 | 0xbfd43 | 0x84000000 | 0xbfd44 | 0x84000000 | 0xbfd45 | 0x84000000 | 0xbfd46 | 0x84000000 | 0xbfd47
1 | way 1 | set 41 | @ 0xbaa40 | 0x84000000 | 0xbfd48 | 0x84000000 | 0xbfd49 | 0x84000000 | 0xbfd4a | 0x84000000 | 0xbfd4b | 0x84000000 | 0xbfd4c | 0x84000000 | 0xbfd4d | 0x84000000 | 0xbfd4e | 0x84000000 | 0xbfd4f
1 | way 1 | set 42 | @ 0xbfc0da80 | 0x666c65 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xf8 | 0 | 0x800000
1 | way 1 | set 43 | @ 0x18ac0 | 0x84000000 | 0xbfd58 | 0x84000000 | 0xbfd59 | 0x84000000 | 0xbfd5a | 0x84000000 | 0xbfd5b | 0x84000000 | 0xbfd5c | 0x84000000 | 0xbfd5d | 0x84000000 | 0xbfd5e | 0x84000000 | 0xbfd5f
1 | way 1 | set 44 | @ 0xbfc0db00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x1620 | 0 | 0x400000 | 0x8b000 | 0
1 | way 1 | set 45 | @ 0xbfc0cb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0x300000 | 0x8e000 | 0x12000 | 0 | 0x8 | 0 | 0x1 | 0x1f | 0x5f676573 | 0x63617473
1 | way 1 | set 46 | @ 0xbfc0db80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x2 | 0x12000 | 0xd | 0x300000 | 0x8e000 | 0 | 0x63617473 | 0x6b
1 | way 1 | set 47 | @ 0xbabc0 | 0x84000000 | 0xbfd78 | 0x84000000 | 0xbfd79 | 0x84000000 | 0xbfd7a | 0x84000000 | 0xbfd7b | 0x84000000 | 0xbfd7c | 0x84000000 | 0xbfd7d | 0x84000000 | 0xbfd7e | 0x84000000 | 0xbfd7f
1 | way 1 | set 48 | @ 0xbfc04c00 | 0x64657465 | 0x20746120 | 0x6c637963 | 0x2065 | 0x4f425b0a | 0x205d544f | 0x20554d4d | 0x69746361 | 0x69746176 | 0x63206e6f | 0x6c706d6f | 0x64657465 | 0x20746120 | 0x6c637963 | 0x2065 | 0x4f425b0a
1 | way 1 | set 49 | @ 0xbfc04c40 | 0x205d544f | 0x65686353 | 0x656c7564 | 0x69207372 | 0x6974696e | 0x73696c61 | 0x6f697461 | 0x6f63206e | 0x656c706d | 0x20646574 | 0x63207461 | 0x656c6379 | 0x20 | 0x8 | 0x8 | 0x8
1 | way 1 | set 50 | @ 0xbfc04c80 | 0x8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 51 | @ 0x6fcc0 | 0x84000000 | 0xbfd98 | 0x84000000 | 0xbfd99 | 0x84000000 | 0xbfd9a | 0x84000000 | 0xbfd9b | 0x84000000 | 0xbfd9c | 0x84000000 | 0xbfd9d | 0x84000000 | 0xbfd9e | 0x84000000 | 0xbfd9f
1 | way 1 | set 52 | @ 0xbad00 | 0x84000000 | 0xbfda0 | 0x84000000 | 0xbfda1 | 0x84000000 | 0xbfda2 | 0x84000000 | 0xbfda3 | 0x84000000 | 0xbfda4 | 0x84000000 | 0xbfda5 | 0x84000000 | 0xbfda6 | 0x84000000 | 0xbfda7
1 | way 1 | set 53 | @ 0xbad40 | 0x84000000 | 0xbfda8 | 0x84000000 | 0xbfda9 | 0x84000000 | 0xbfdaa | 0x84000000 | 0xbfdab | 0x84000000 | 0xbfdac | 0x84000000 | 0xbfdad | 0x84000000 | 0xbfdae | 0x84000000 | 0xbfdaf
1 | way 1 | set 54 | @ 0xbfc04d80 | 0x10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 55 | @ 0xbfc0ddc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x6 | 0x10000
1 | way 1 | set 56 | @ 0xbae00 | 0x84000000 | 0xbfdc0 | 0x84000000 | 0xbfdc1 | 0x84000000 | 0xbfdc2 | 0x84000000 | 0xbfdc3 | 0x84000000 | 0xbfdc4 | 0x84000000 | 0xbfdc5 | 0x84000000 | 0xbfdc6 | 0x84000000 | 0xbfdc7
1 | way 1 | set 57 | @ 0xbfc0de40 | 0 | 0x1 | 0 | 0 | 0 | 0x736e6f63 | 0x72656d75 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x1 | 0x4
1 | way 1 | set 58 | @ 0xbfc0de80 | 0xffffffff | 0x1 | 0x1 | 0 | 0 | 0 | 0x74756f72 | 0x415f7265 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x2
1 | way 1 | set 59 | @ 0xbfc0aec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xf00 | 0
1 | way 1 | set 60 | @ 0xbfc0af00 | 0xbc | 0 | 0 | 0xbfc0af10 | 0 | 0 | 0x2f | 0x1 | 0 | 0 | 0 | 0 | 0 | 0 | 0x20000 | 0x24
1 | way 1 | set 61 | @ 0xbfc04f40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x1000 | 0x2000
1 | way 1 | set 62 | @ 0xbfc04f80 | 0x3000 | 0x12000 | 0x68000 | 0x8e000 | 0xb4000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 63 | @ 0xbfc0dfc0 | 0 | 0 | 0 | 0 | 0x3 | 0xffffffff | 0 | 0x1 | 0 | 0 | 0x1 | 0x19 | 0 | 0x1 | 0x19 | 0x1
1 | way 2 | set 0 | @ 0xba000 | 0xae000000 | 0xbfc00 | 0x8e000000 | 0xbfc01 | 0x8e000000 | 0xbfc02 | 0xae000000 | 0xbfc03 | 0xae000000 | 0xbfc04 | 0x8e000000 | 0xbfc05 | 0 | 0 | 0 | 0
1 | way 2 | set 1 | @ 0x18040 | 0x8c000000 | 0xbfc08 | 0x8c000000 | 0xbfc09 | 0xac400000 | 0xbfc0a | 0x8c000000 | 0xbfc0b | 0xac000000 | 0xbfc0c | 0xac000000 | 0xbfc0d | 0xac000000 | 0xbfc0e | 0 | 0
1 | way 2 | set 2 | @ 0xbc080 | 0x84000000 | 0xbfe10 | 0x84000000 | 0xbfe11 | 0x84000000 | 0xbfe12 | 0x84000000 | 0xbfe13 | 0x84000000 | 0xbfe14 | 0x84000000 | 0xbfe15 | 0x84000000 | 0xbfe16 | 0x84000000 | 0xbfe17
1 | way 2 | set 3 | @ 0x930c0 | 0x8d000000 | 0xa8 | 0x8d000000 | 0xa9 | 0x8d000000 | 0xaa | 0x8d000000 | 0xab | 0x8d000000 | 0xac | 0x8d000000 | 0xad | 0x8d000000 | 0xae | 0x8d000000 | 0xaf
1 | way 2 | set 4 | @ 0xbfc0c100 | 0 | 0 | 0 | 0 | 0 | 0xbfd00000 | 0x200000 | 0x2 | 0 | 0xbfd00000 | 0x47455350 | 0x5543495f | 0 | 0 | 0 | 0
1 | way 2 | set 5 | @ 0xbc140 | 0x84000000 | 0xbfe28 | 0x84000000 | 0xbfe29 | 0x84000000 | 0xbfe2a | 0x84000000 | 0xbfe2b | 0x84000000 | 0xbfe2c | 0x84000000 | 0xbfe2d | 0x84000000 | 0xbfe2e | 0x84000000 | 0xbfe2f
1 | way 2 | set 6 | @ 0xbfc0c180 | 0x1000 | 0x2 | 0 | 0xbff10000 | 0x47455350 | 0x5954545f | 0 | 0 | 0 | 0 | 0 | 0 | 0xbff20000 | 0x1000 | 0x2 | 0
1 | way 2 | set 7 | @ 0x961c0 | 0x84000000 | 0xbfe38 | 0x84000000 | 0xbfe39 | 0x84000000 | 0xbfe3a | 0x84000000 | 0xbfe3b | 0x84000000 | 0xbfe3c | 0x84000000 | 0xbfe3d | 0x84000000 | 0xbfe3e | 0x84000000 | 0xbfe3f
1 | way 2 | set 8 | @ 0xbc200 | 0x84000000 | 0xbfe40 | 0x84000000 | 0xbfe41 | 0x84000000 | 0xbfe42 | 0x84000000 | 0xbfe43 | 0x84000000 | 0xbfe44 | 0x84000000 | 0xbfe45 | 0x84000000 | 0xbfe46 | 0x84000000 | 0xbfe47
1 | way 2 | set 9 | @ 0xbc240 | 0x84000000 | 0xbfe48 | 0x84000000 | 0xbfe49 | 0x84000000 | 0xbfe4a | 0x84000000 | 0xbfe4b | 0x84000000 | 0xbfe4c | 0x84000000 | 0xbfe4d | 0x84000000 | 0xbfe4e | 0x84000000 | 0xbfe4f
1 | way 2 | set 10 | @ 0xbc280 | 0x84000000 | 0xbfe50 | 0x84000000 | 0xbfe51 | 0x84000000 | 0xbfe52 | 0x84000000 | 0xbfe53 | 0x84000000 | 0xbfe54 | 0x84000000 | 0xbfe55 | 0x84000000 | 0xbfe56 | 0x84000000 | 0xbfe57
1 | way 2 | set 11 | @ 0xbfc0c2c0 | 0 | 0xff0000 | 0x74756f72 | 0x7265 | 0 | 0 | 0 | 0 | 0 | 0x20000000 | 0 | 0x8 | 0x9 | 0x4 | 0xf | 0xf
1 | way 2 | set 12 | @ 0xbfc0c300 | 0 | 0x6c6c6568 | 0x6f | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x5 | 0x5 | 0x1 | 0x17 | 0x18 | 0x4
1 | way 2 | set 13 | @ 0x6e340 | 0x84000000 | 0xbfe68 | 0x84000000 | 0xbfe69 | 0x84000000 | 0xbfe6a | 0x84000000 | 0xbfe6b | 0x84000000 | 0xbfe6c | 0x84000000 | 0xbfe6d | 0x84000000 | 0xbfe6e | 0x84000000 | 0xbfe6f
1 | way 2 | set 14 | @ 0xbc380 | 0x84000000 | 0xbfe70 | 0x84000000 | 0xbfe71 | 0x84000000 | 0xbfe72 | 0x84000000 | 0xbfe73 | 0x84000000 | 0xbfe74 | 0x84000000 | 0xbfe75 | 0x84000000 | 0xbfe76 | 0x84000000 | 0xbfe77
1 | way 2 | set 15 | @ 0xbc3c0 | 0x84000000 | 0xbfe78 | 0x84000000 | 0xbfe79 | 0x84000000 | 0xbfe7a | 0x84000000 | 0xbfe7b | 0x84000000 | 0xbfe7c | 0x84000000 | 0xbfe7d | 0x84000000 | 0xbfe7e | 0x84000000 | 0xbfe7f
1 | way 2 | set 16 | @ 0xbc400 | 0x84000000 | 0xbfe80 | 0x84000000 | 0xbfe81 | 0x84000000 | 0xbfe82 | 0x84000000 | 0xbfe83 | 0x84000000 | 0xbfe84 | 0x84000000 | 0xbfe85 | 0x84000000 | 0xbfe86 | 0x84000000 | 0xbfe87
1 | way 2 | set 17 | @ 0xbc440 | 0x84000000 | 0xbfe88 | 0x84000000 | 0xbfe89 | 0x84000000 | 0xbfe8a | 0x84000000 | 0xbfe8b | 0x84000000 | 0xbfe8c | 0x84000000 | 0xbfe8d | 0x84000000 | 0xbfe8e | 0x84000000 | 0xbfe8f
1 | way 2 | set 18 | @ 0xbc480 | 0x84000000 | 0xbfe90 | 0x84000000 | 0xbfe91 | 0x84000000 | 0xbfe92 | 0x84000000 | 0xbfe93 | 0x84000000 | 0xbfe94 | 0x84000000 | 0xbfe95 | 0x84000000 | 0xbfe96 | 0x84000000 | 0xbfe97
1 | way 2 | set 19 | @ 0x6e4c0 | 0x84000000 | 0xbfe98 | 0x84000000 | 0xbfe99 | 0x84000000 | 0xbfe9a | 0x84000000 | 0xbfe9b | 0x84000000 | 0xbfe9c | 0x84000000 | 0xbfe9d | 0x84000000 | 0xbfe9e | 0x84000000 | 0xbfe9f
1 | way 2 | set 20 | @ 0xbc500 | 0x84000000 | 0xbfea0 | 0x84000000 | 0xbfea1 | 0x84000000 | 0xbfea2 | 0x84000000 | 0xbfea3 | 0x84000000 | 0xbfea4 | 0x84000000 | 0xbfea5 | 0x84000000 | 0xbfea6 | 0x84000000 | 0xbfea7
1 | way 2 | set 21 | @ 0x6e540 | 0x84000000 | 0xbfea8 | 0x84000000 | 0xbfea9 | 0x84000000 | 0xbfeaa | 0x84000000 | 0xbfeab | 0x84000000 | 0xbfeac | 0x84000000 | 0xbfead | 0x84000000 | 0xbfeae | 0x84000000 | 0xbfeaf
1 | way 2 | set 22 | @ 0xbc580 | 0x84000000 | 0xbfeb0 | 0x84000000 | 0xbfeb1 | 0x84000000 | 0xbfeb2 | 0x84000000 | 0xbfeb3 | 0x84000000 | 0xbfeb4 | 0x84000000 | 0xbfeb5 | 0x84000000 | 0xbfeb6 | 0x84000000 | 0xbfeb7
1 | way 2 | set 23 | @ 0x6e5c0 | 0x84000000 | 0xbfeb8 | 0x84000000 | 0xbfeb9 | 0x84000000 | 0xbfeba | 0x84000000 | 0xbfebb | 0x84000000 | 0xbfebc | 0x84000000 | 0xbfebd | 0x84000000 | 0xbfebe | 0x84000000 | 0xbfebf
1 | way 2 | set 24 | @ 0xbc600 | 0x84000000 | 0xbfec0 | 0x84000000 | 0xbfec1 | 0x84000000 | 0xbfec2 | 0x84000000 | 0xbfec3 | 0x84000000 | 0xbfec4 | 0x84000000 | 0xbfec5 | 0x84000000 | 0xbfec6 | 0x84000000 | 0xbfec7
1 | way 2 | set 25 | @ 0xbc640 | 0x84000000 | 0xbfec8 | 0x84000000 | 0xbfec9 | 0x84000000 | 0xbfeca | 0x84000000 | 0xbfecb | 0x84000000 | 0xbfecc | 0x84000000 | 0xbfecd | 0x84000000 | 0xbfece | 0x84000000 | 0xbfecf
1 | way 2 | set 26 | @ 0xbc680 | 0x84000000 | 0xbfed0 | 0x84000000 | 0xbfed1 | 0x84000000 | 0xbfed2 | 0x84000000 | 0xbfed3 | 0x84000000 | 0xbfed4 | 0x84000000 | 0xbfed5 | 0x84000000 | 0xbfed6 | 0x84000000 | 0xbfed7
1 | way 2 | set 27 | @ 0xbc6c0 | 0x84000000 | 0xbfed8 | 0x84000000 | 0xbfed9 | 0x84000000 | 0xbfeda | 0x84000000 | 0xbfedb | 0x84000000 | 0xbfedc | 0x84000000 | 0xbfedd | 0x84000000 | 0xbfede | 0x84000000 | 0xbfedf
1 | way 2 | set 28 | @ 0x6e700 | 0x84000000 | 0xbfee0 | 0x84000000 | 0xbfee1 | 0x84000000 | 0xbfee2 | 0x84000000 | 0xbfee3 | 0x84000000 | 0xbfee4 | 0x84000000 | 0xbfee5 | 0x84000000 | 0xbfee6 | 0x84000000 | 0xbfee7
1 | way 2 | set 29 | @ 0xbc740 | 0x84000000 | 0xbfee8 | 0x84000000 | 0xbfee9 | 0x84000000 | 0xbfeea | 0x84000000 | 0xbfeeb | 0x84000000 | 0xbfeec | 0x84000000 | 0xbfeed | 0x84000000 | 0xbfeee | 0x84000000 | 0xbfeef
1 | way 2 | set 30 | @ 0x6e780 | 0x84000000 | 0xbfef0 | 0x84000000 | 0xbfef1 | 0x84000000 | 0xbfef2 | 0x84000000 | 0xbfef3 | 0x84000000 | 0xbfef4 | 0x84000000 | 0xbfef5 | 0x84000000 | 0xbfef6 | 0x84000000 | 0xbfef7
1 | way 2 | set 31 | @ 0xb57c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xc00000ba | 0xc00000bc
1 | way 2 | set 32 | @ 0xbd800 | 0x84000000 | 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 33 | @ 0x92840 | 0x88000000 | 0x96 | 0x88000000 | 0x97 | 0x88000000 | 0x98 | 0x88000000 | 0x99 | 0x88000000 | 0x9a | 0x88000000 | 0x9b | 0x88000000 | 0x9c | 0x88000000 | 0x9d
1 | way 2 | set 34 | @ 0xbc880 | 0x84000000 | 0xbff10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 35 | @ 0xbfc0d8c0 | 0 | 0 | 0 | 0 | 0 | 0x1578 | 0 | 0x400000 | 0x66000 | 0 | 0x62617470 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 36 | @ 0x96900 | 0x84000000 | 0xbff20 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 37 | @ 0xbfc04940 | 0x4e495b0a | 0x45205449 | 0x524f5252 | 0x694d205d | 0x6e697373 | 0x54502067 | 0x66204241 | 0x7620726f | 0x63617073 | 0x2065 | 0xbfc02cf0 | 0xbfc02cf0 | 0xbfc02c44 | 0xbfc02ca0 | 0xbfc02a90 | 0xbfc02b98
1 | way 2 | set 38 | @ 0x97980 | 0x84000000 | 0xf30 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 39 | @ 0xbfc0d9c0 | 0x6 | 0x10000 | 0 | 0x10000 | 0x7a000 | 0 | 0x5f63696e | 0x32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 40 | @ 0xbfc0da00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x6 | 0x4000
1 | way 2 | set 41 | @ 0x18a40 | 0x84000000 | 0xbfd48 | 0x84000000 | 0xbfd49 | 0x84000000 | 0xbfd4a | 0x84000000 | 0xbfd4b | 0x84000000 | 0xbfd4c | 0x84000000 | 0xbfd4d | 0x84000000 | 0xbfd4e | 0x84000000 | 0xbfd4f
1 | way 2 | set 42 | @ 0x71a80 | 0x84000000 | 0xf50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 43 | @ 0x6fac0 | 0x84000000 | 0xbfd58 | 0x84000000 | 0xbfd59 | 0x84000000 | 0xbfd5a | 0x84000000 | 0xbfd5b | 0x84000000 | 0xbfd5c | 0x84000000 | 0xbfd5d | 0x84000000 | 0xbfd5e | 0x84000000 | 0xbfd5f
1 | way 2 | set 44 | @ 0x94b00 | 0x84000000 | 0xbfd60 | 0x84000000 | 0xbfd61 | 0x84000000 | 0xbfd62 | 0x84000000 | 0xbfd63 | 0x84000000 | 0xbfd64 | 0x84000000 | 0xbfd65 | 0x84000000 | 0xbfd66 | 0x84000000 | 0xbfd67
1 | way 2 | set 45 | @ 0xbab40 | 0x84000000 | 0xbfd68 | 0x84000000 | 0xbfd69 | 0x84000000 | 0xbfd6a | 0x84000000 | 0xbfd6b | 0x84000000 | 0xbfd6c | 0x84000000 | 0xbfd6d | 0x84000000 | 0xbfd6e | 0x84000000 | 0xbfd6f
1 | way 2 | set 46 | @ 0xbab80 | 0x84000000 | 0xbfd70 | 0x84000000 | 0xbfd71 | 0x84000000 | 0xbfd72 | 0x84000000 | 0xbfd73 | 0x84000000 | 0xbfd74 | 0x84000000 | 0xbfd75 | 0x84000000 | 0xbfd76 | 0x84000000 | 0xbfd77
1 | way 2 | set 47 | @ 0xbfc04bc0 | 0x6d6f6320 | 0x74656c70 | 0x61206465 | 0x79632074 | 0x20656c63 | 0x203a | 0x4f425b0a | 0x205d544f | 0x69726550 | 0x72656870 | 0x20736c61 | 0x74696e69 | 0x696c6169 | 0x69746173 | 0x63206e6f | 0x6c706d6f
1 | way 2 | set 48 | @ 0xbac00 | 0x84000000 | 0xbfd80 | 0x84000000 | 0xbfd81 | 0x84000000 | 0xbfd82 | 0x84000000 | 0xbfd83 | 0x84000000 | 0xbfd84 | 0x84000000 | 0xbfd85 | 0x84000000 | 0xbfd86 | 0x84000000 | 0xbfd87
1 | way 2 | set 49 | @ 0x94c40 | 0x84000000 | 0xbfd88 | 0x84000000 | 0xbfd89 | 0x84000000 | 0xbfd8a | 0x84000000 | 0xbfd8b | 0x84000000 | 0xbfd8c | 0x84000000 | 0xbfd8d | 0x84000000 | 0xbfd8e | 0x84000000 | 0xbfd8f
1 | way 2 | set 50 | @ 0xbfc0cc80 | 0x6b | 0 | 0 | 0 | 0 | 0 | 0x10000 | 0xc6000 | 0x10000 | 0 | 0xb | 0 | 0x1 | 0x24 | 0x746f6f62 | 0x646f635f
1 | way 2 | set 51 | @ 0x94cc0 | 0x84000000 | 0xbfd98 | 0x84000000 | 0xbfd99 | 0x84000000 | 0xbfd9a | 0x84000000 | 0xbfd9b | 0x84000000 | 0xbfd9c | 0x84000000 | 0xbfd9d | 0x84000000 | 0xbfd9e | 0x84000000 | 0xbfd9f
1 | way 2 | set 52 | @ 0x94d00 | 0x84000000 | 0xbfda0 | 0x84000000 | 0xbfda1 | 0x84000000 | 0xbfda2 | 0x84000000 | 0xbfda3 | 0x84000000 | 0xbfda4 | 0x84000000 | 0xbfda5 | 0x84000000 | 0xbfda6 | 0x84000000 | 0xbfda7
1 | way 2 | set 53 | @ 0x6fd40 | 0x84000000 | 0xbfda8 | 0x84000000 | 0xbfda9 | 0x84000000 | 0xbfdaa | 0x84000000 | 0xbfdab | 0x84000000 | 0xbfdac | 0x84000000 | 0xbfdad | 0x84000000 | 0xbfdae | 0x84000000 | 0xbfdaf
1 | way 2 | set 54 | @ 0xbad80 | 0x84000000 | 0xbfdb0 | 0x84000000 | 0xbfdb1 | 0x84000000 | 0xbfdb2 | 0x84000000 | 0xbfdb3 | 0x84000000 | 0xbfdb4 | 0x84000000 | 0xbfdb5 | 0x84000000 | 0xbfdb6 | 0x84000000 | 0xbfdb7
1 | way 2 | set 55 | @ 0x6fdc0 | 0x84000000 | 0xbfdb8 | 0x84000000 | 0xbfdb9 | 0x84000000 | 0xbfdba | 0x84000000 | 0xbfdbb | 0x84000000 | 0xbfdbc | 0x84000000 | 0xbfdbd | 0x84000000 | 0xbfdbe | 0x84000000 | 0xbfdbf
1 | way 2 | set 56 | @ 0xbfc0de00 | 0 | 0x10000 | 0xc6000 | 0 | 0x646f7270 | 0x72656375 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x1 | 0x3 | 0xffffffff
1 | way 2 | set 57 | @ 0x94e40 | 0x84000000 | 0xbfdc8 | 0x84000000 | 0xbfdc9 | 0x84000000 | 0xbfdca | 0x84000000 | 0xbfdcb | 0x84000000 | 0xbfdcc | 0x84000000 | 0xbfdcd | 0x84000000 | 0xbfdce | 0x84000000 | 0xbfdcf
1 | way 2 | set 58 | @ 0xbfc04e80 | 0x300000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 59 | @ 0xbfc0dec0 | 0x5 | 0xffffffff | 0x2 | 0x1 | 0 | 0 | 0 | 0x74756f72 | 0x425f7265 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 60 | @ 0x2f00 | 0x2 | 0 | 0 | 0 | 0x101 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 61 | @ 0xbaf40 | 0x84000000 | 0xbfde8 | 0x84000000 | 0xbfde9 | 0x84000000 | 0xbfdea | 0x84000000 | 0xbfdeb | 0x84000000 | 0xbfdec | 0x84000000 | 0xbfded | 0x84000000 | 0xbfdee | 0x84000000 | 0xbfdef
1 | way 2 | set 62 | @ 0xbfc0df80 | 0 | 0 | 0x3 | 0x3 | 0xffffffff | 0 | 0x1 | 0 | 0 | 0 | 0x6e69616d | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 63 | @ 0xbafc0 | 0x84000000 | 0xbfdf8 | 0x84000000 | 0xbfdf9 | 0x84000000 | 0xbfdfa | 0x84000000 | 0xbfdfb | 0x84000000 | 0xbfdfc | 0x84000000 | 0xbfdfd | 0x84000000 | 0xbfdfe | 0x84000000 | 0xbfdff
1 | way 3 | set 0 | @ 0xb0000 | 0x400000 | 0x2a2a200a | 0x6d69202a | 0x20656761 | 0x2a206425 | 0x61202a2a | 0x61642074 | 0x3d206574 | 0x20642520 | 0xa | 0x65686365 | 0x69672063 | 0x695f7465 | 0x725f636f | 0x20646165 | 0x61206425
1 | way 3 | set 1 | @ 0x6f040 | 0x8c000000 | 0xbfc08 | 0x8c000000 | 0xbfc09 | 0xac400000 | 0xbfc0a | 0x8c000000 | 0xbfc0b | 0xac000000 | 0xbfc0c | 0xac000000 | 0xbfc0d | 0x8c000000 | 0xbfc0e | 0 | 0
1 | way 3 | set 2 | @ 0x96080 | 0x84000000 | 0xbfe10 | 0x84000000 | 0xbfe11 | 0x84000000 | 0xbfe12 | 0x84000000 | 0xbfe13 | 0x84000000 | 0xbfe14 | 0x84000000 | 0xbfe15 | 0x84000000 | 0xbfe16 | 0x84000000 | 0xbfe17
1 | way 3 | set 3 | @ 0xbc0c0 | 0x84000000 | 0xbfe18 | 0x84000000 | 0xbfe19 | 0x84000000 | 0xbfe1a | 0x84000000 | 0xbfe1b | 0x84000000 | 0xbfe1c | 0x84000000 | 0xbfe1d | 0x84000000 | 0xbfe1e | 0x84000000 | 0xbfe1f
1 | way 3 | set 4 | @ 0x6e100 | 0x84000000 | 0xbfe20 | 0x84000000 | 0xbfe21 | 0x84000000 | 0xbfe22 | 0x84000000 | 0xbfe23 | 0x84000000 | 0xbfe24 | 0x84000000 | 0xbfe25 | 0x84000000 | 0xbfe26 | 0x84000000 | 0xbfe27
1 | way 3 | set 5 | @ 0x1a140 | 0x84000000 | 0xbfe28 | 0x84000000 | 0xbfe29 | 0x84000000 | 0xbfe2a | 0x84000000 | 0xbfe2b | 0x84000000 | 0xbfe2c | 0x84000000 | 0xbfe2d | 0x84000000 | 0xbfe2e | 0x84000000 | 0xbfe2f
1 | way 3 | set 6 | @ 0x6e180 | 0x84000000 | 0xbfe30 | 0x84000000 | 0xbfe31 | 0x84000000 | 0xbfe32 | 0x84000000 | 0xbfe33 | 0x84000000 | 0xbfe34 | 0x84000000 | 0xbfe35 | 0x84000000 | 0xbfe36 | 0x84000000 | 0xbfe37
1 | way 3 | set 7 | @ 0xbfc0c1c0 | 0xbff20000 | 0x47455350 | 0x414d445f | 0 | 0 | 0 | 0 | 0 | 0 | 0xf30000 | 0x1000 | 0x2 | 0 | 0xf30000 | 0x47455350 | 0x43494e5f
1 | way 3 | set 8 | @ 0x1a200 | 0x84000000 | 0xbfe40 | 0x84000000 | 0xbfe41 | 0x84000000 | 0xbfe42 | 0x84000000 | 0xbfe43 | 0x84000000 | 0xbfe44 | 0x84000000 | 0xbfe45 | 0x84000000 | 0xbfe46 | 0x84000000 | 0xbfe47
1 | way 3 | set 9 | @ 0x1a240 | 0x84000000 | 0xbfe48 | 0x84000000 | 0xbfe49 | 0x84000000 | 0xbfe4a | 0x84000000 | 0xbfe4b | 0x84000000 | 0xbfe4c | 0x84000000 | 0xbfe4d | 0x84000000 | 0xbfe4e | 0x84000000 | 0xbfe4f
1 | way 3 | set 10 | @ 0x1a280 | 0x84000000 | 0xbfe50 | 0x84000000 | 0xbfe51 | 0x84000000 | 0xbfe52 | 0x84000000 | 0xbfe53 | 0x84000000 | 0xbfe54 | 0x84000000 | 0xbfe55 | 0x84000000 | 0xbfe56 | 0x84000000 | 0xbfe57
1 | way 3 | set 11 | @ 0x6e2c0 | 0x84000000 | 0xbfe58 | 0x84000000 | 0xbfe59 | 0x84000000 | 0xbfe5a | 0x84000000 | 0xbfe5b | 0x84000000 | 0xbfe5c | 0x84000000 | 0xbfe5d | 0x84000000 | 0xbfe5e | 0x84000000 | 0xbfe5f
1 | way 3 | set 12 | @ 0x6e300 | 0x84000000 | 0xbfe60 | 0x84000000 | 0xbfe61 | 0x84000000 | 0xbfe62 | 0x84000000 | 0xbfe63 | 0x84000000 | 0xbfe64 | 0x84000000 | 0xbfe65 | 0x84000000 | 0xbfe66 | 0x84000000 | 0xbfe67
1 | way 3 | set 13 | @ 0x96340 | 0x84000000 | 0xbfe68 | 0x84000000 | 0xbfe69 | 0x84000000 | 0xbfe6a | 0x84000000 | 0xbfe6b | 0x84000000 | 0xbfe6c | 0x84000000 | 0xbfe6d | 0x84000000 | 0xbfe6e | 0x84000000 | 0xbfe6f
1 | way 3 | set 14 | @ 0x6e380 | 0x84000000 | 0xbfe70 | 0x84000000 | 0xbfe71 | 0x84000000 | 0xbfe72 | 0x84000000 | 0xbfe73 | 0x84000000 | 0xbfe74 | 0x84000000 | 0xbfe75 | 0x84000000 | 0xbfe76 | 0x84000000 | 0xbfe77
1 | way 3 | set 15 | @ 0x6e3c0 | 0x84000000 | 0xbfe78 | 0x84000000 | 0xbfe79 | 0x84000000 | 0xbfe7a | 0x84000000 | 0xbfe7b | 0x84000000 | 0xbfe7c | 0x84000000 | 0xbfe7d | 0x84000000 | 0xbfe7e | 0x84000000 | 0xbfe7f
1 | way 3 | set 16 | @ 0x96400 | 0x84000000 | 0xbfe80 | 0x84000000 | 0xbfe81 | 0x84000000 | 0xbfe82 | 0x84000000 | 0xbfe83 | 0x84000000 | 0xbfe84 | 0x84000000 | 0xbfe85 | 0x84000000 | 0xbfe86 | 0x84000000 | 0xbfe87
1 | way 3 | set 17 | @ 0x6e440 | 0x84000000 | 0xbfe88 | 0x84000000 | 0xbfe89 | 0x84000000 | 0xbfe8a | 0x84000000 | 0xbfe8b | 0x84000000 | 0xbfe8c | 0x84000000 | 0xbfe8d | 0x84000000 | 0xbfe8e | 0x84000000 | 0xbfe8f
1 | way 3 | set 18 | @ 0x96480 | 0x84000000 | 0xbfe90 | 0x84000000 | 0xbfe91 | 0x84000000 | 0xbfe92 | 0x84000000 | 0xbfe93 | 0x84000000 | 0xbfe94 | 0x84000000 | 0xbfe95 | 0x84000000 | 0xbfe96 | 0x84000000 | 0xbfe97
1 | way 3 | set 19 | @ 0x964c0 | 0x84000000 | 0xbfe98 | 0x84000000 | 0xbfe99 | 0x84000000 | 0xbfe9a | 0x84000000 | 0xbfe9b | 0x84000000 | 0xbfe9c | 0x84000000 | 0xbfe9d | 0x84000000 | 0xbfe9e | 0x84000000 | 0xbfe9f
1 | way 3 | set 20 | @ 0x6e500 | 0x84000000 | 0xbfea0 | 0x84000000 | 0xbfea1 | 0x84000000 | 0xbfea2 | 0x84000000 | 0xbfea3 | 0x84000000 | 0xbfea4 | 0x84000000 | 0xbfea5 | 0x84000000 | 0xbfea6 | 0x84000000 | 0xbfea7
1 | way 3 | set 21 | @ 0x96540 | 0x84000000 | 0xbfea8 | 0x84000000 | 0xbfea9 | 0x84000000 | 0xbfeaa | 0x84000000 | 0xbfeab | 0x84000000 | 0xbfeac | 0x84000000 | 0xbfead | 0x84000000 | 0xbfeae | 0x84000000 | 0xbfeaf
1 | way 3 | set 22 | @ 0x6e580 | 0x84000000 | 0xbfeb0 | 0x84000000 | 0xbfeb1 | 0x84000000 | 0xbfeb2 | 0x84000000 | 0xbfeb3 | 0x84000000 | 0xbfeb4 | 0x84000000 | 0xbfeb5 | 0x84000000 | 0xbfeb6 | 0x84000000 | 0xbfeb7
1 | way 3 | set 23 | @ 0x965c0 | 0x84000000 | 0xbfeb8 | 0x84000000 | 0xbfeb9 | 0x84000000 | 0xbfeba | 0x84000000 | 0xbfebb | 0x84000000 | 0xbfebc | 0x84000000 | 0xbfebd | 0x84000000 | 0xbfebe | 0x84000000 | 0xbfebf
1 | way 3 | set 24 | @ 0x6e600 | 0x84000000 | 0xbfec0 | 0x84000000 | 0xbfec1 | 0x84000000 | 0xbfec2 | 0x84000000 | 0xbfec3 | 0x84000000 | 0xbfec4 | 0x84000000 | 0xbfec5 | 0x84000000 | 0xbfec6 | 0x84000000 | 0xbfec7
1 | way 3 | set 25 | @ 0x6e640 | 0x84000000 | 0xbfec8 | 0x84000000 | 0xbfec9 | 0x84000000 | 0xbfeca | 0x84000000 | 0xbfecb | 0x84000000 | 0xbfecc | 0x84000000 | 0xbfecd | 0x84000000 | 0xbfece | 0x84000000 | 0xbfecf
1 | way 3 | set 26 | @ 0x6e680 | 0x84000000 | 0xbfed0 | 0x84000000 | 0xbfed1 | 0x84000000 | 0xbfed2 | 0x84000000 | 0xbfed3 | 0x84000000 | 0xbfed4 | 0x84000000 | 0xbfed5 | 0x84000000 | 0xbfed6 | 0x84000000 | 0xbfed7
1 | way 3 | set 27 | @ 0x6e6c0 | 0x84000000 | 0xbfed8 | 0x84000000 | 0xbfed9 | 0x84000000 | 0xbfeda | 0x84000000 | 0xbfedb | 0x84000000 | 0xbfedc | 0x84000000 | 0xbfedd | 0x84000000 | 0xbfede | 0x84000000 | 0xbfedf
1 | way 3 | set 28 | @ 0x96700 | 0x84000000 | 0xbfee0 | 0x84000000 | 0xbfee1 | 0x84000000 | 0xbfee2 | 0x84000000 | 0xbfee3 | 0x84000000 | 0xbfee4 | 0x84000000 | 0xbfee5 | 0x84000000 | 0xbfee6 | 0x84000000 | 0xbfee7
1 | way 3 | set 29 | @ 0x6e740 | 0x84000000 | 0xbfee8 | 0x84000000 | 0xbfee9 | 0x84000000 | 0xbfeea | 0x84000000 | 0xbfeeb | 0x84000000 | 0xbfeec | 0x84000000 | 0xbfeed | 0x84000000 | 0xbfeee | 0x84000000 | 0xbfeef
1 | way 3 | set 30 | @ 0x96780 | 0x84000000 | 0xbfef0 | 0x84000000 | 0xbfef1 | 0x84000000 | 0xbfef2 | 0x84000000 | 0xbfef3 | 0x84000000 | 0xbfef4 | 0x84000000 | 0xbfef5 | 0x84000000 | 0xbfef6 | 0x84000000 | 0xbfef7
1 | way 3 | set 31 | @ 0x137c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xc0000018 | 0xc000001a
1 | way 3 | set 32 | @ 0x97800 | 0x84000000 | 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 3 | set 33 | @ 0xba840 | 0x84000000 | 0xbfd08 | 0x84000000 | 0xbfd09 | 0x84000000 | 0xbfd0a | 0x84000000 | 0xbfd0b | 0x84000000 | 0xbfd0c | 0x84000000 | 0xbfd0d | 0x84000000 | 0xbfd0e | 0x84000000 | 0xbfd0f
1 | way 3 | set 34 | @ 0x96880 | 0x84000000 | 0xbff10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 3 | set 35 | @ 0x6f8c0 | 0x84000000 | 0xbfd18 | 0x84000000 | 0xbfd19 | 0x84000000 | 0xbfd1a | 0x84000000 | 0xbfd1b | 0x84000000 | 0xbfd1c | 0x84000000 | 0xbfd1d | 0x84000000 | 0xbfd1e | 0x84000000 | 0xbfd1f
1 | way 3 | set 36 | @ 0x1a900 | 0xa4400000 | 0xbff20 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 3 | set 37 | @ 0x6f940 | 0x84000000 | 0xbfd28 | 0x84000000 | 0xbfd29 | 0x84000000 | 0xbfd2a | 0x84000000 | 0xbfd2b | 0x84000000 | 0xbfd2c | 0x84000000 | 0xbfd2d | 0x84000000 | 0xbfd2e | 0x84000000 | 0xbfd2f
1 | way 3 | set 38 | @ 0xbfc04980 | 0xbfc02cf0 | 0xbfc02b28 | 0xbfc02c54 | 0xbfc02bc8 | 0x4f425b0a | 0x4520544f | 0x524f5252 | 0x694d205d | 0x6e697373 | 0x41522067 | 0x7370204d | 0x69206765 | 0x6c63206e | 0x65747375 | 0x2072 | 0x4f425b0a
1 | way 3 | set 39 | @ 0x6f9c0 | 0x84000000 | 0xbfd38 | 0x84000000 | 0xbfd39 | 0x84000000 | 0xbfd3a | 0x84000000 | 0xbfd3b | 0x84000000 | 0xbfd3c | 0x84000000 | 0xbfd3d | 0x84000000 | 0xbfd3e | 0x84000000 | 0xbfd3f
1 | way 3 | set 40 | @ 0x6fa00 | 0x84000000 | 0xbfd40 | 0x84000000 | 0xbfd41 | 0x84000000 | 0xbfd42 | 0x84000000 | 0xbfd43 | 0x84000000 | 0xbfd44 | 0x84000000 | 0xbfd45 | 0x84000000 | 0xbfd46 | 0x84000000 | 0xbfd47
1 | way 3 | set 41 | @ 0x6fa40 | 0x84000000 | 0xbfd48 | 0x84000000 | 0xbfd49 | 0x84000000 | 0xbfd4a | 0x84000000 | 0xbfd4b | 0x84000000 | 0xbfd4c | 0x84000000 | 0xbfd4d | 0x84000000 | 0xbfd4e | 0x84000000 | 0xbfd4f
1 | way 3 | set 42 | @ 0xbaa80 | 0x84000000 | 0xbfd50 | 0x84000000 | 0xbfd51 | 0x84000000 | 0xbfd52 | 0x84000000 | 0xbfd53 | 0x84000000 | 0xbfd54 | 0x84000000 | 0xbfd55 | 0x84000000 | 0xbfd56 | 0x84000000 | 0xbfd57
1 | way 3 | set 43 | @ 0x94ac0 | 0x84000000 | 0xbfd58 | 0x84000000 | 0xbfd59 | 0x84000000 | 0xbfd5a | 0x84000000 | 0xbfd5b | 0x84000000 | 0xbfd5c | 0x84000000 | 0xbfd5d | 0x84000000 | 0xbfd5e | 0x84000000 | 0xbfd5f
1 | way 3 | set 44 | @ 0x18b00 | 0x84000000 | 0xbfd60 | 0x84000000 | 0xbfd61 | 0x84000000 | 0xbfd62 | 0x84000000 | 0xbfd63 | 0x84000000 | 0xbfd64 | 0x84000000 | 0xbfd65 | 0x84000000 | 0xbfd66 | 0x84000000 | 0xbfd67
1 | way 3 | set 45 | @ 0x6fb40 | 0x84000000 | 0xbfd68 | 0x84000000 | 0xbfd69 | 0x84000000 | 0xbfd6a | 0x84000000 | 0xbfd6b | 0x84000000 | 0xbfd6c | 0x84000000 | 0xbfd6d | 0x84000000 | 0xbfd6e | 0x84000000 | 0xbfd6f
1 | way 3 | set 46 | @ 0x6fb80 | 0x84000000 | 0xbfd70 | 0x84000000 | 0xbfd71 | 0x84000000 | 0xbfd72 | 0x84000000 | 0xbfd73 | 0x84000000 | 0xbfd74 | 0x84000000 | 0xbfd75 | 0x84000000 | 0xbfd76 | 0x84000000 | 0xbfd77
1 | way 3 | set 47 | @ 0x94bc0 | 0x84000000 | 0xbfd78 | 0x84000000 | 0xbfd79 | 0x84000000 | 0xbfd7a | 0x84000000 | 0xbfd7b | 0x84000000 | 0xbfd7c | 0x84000000 | 0xbfd7d | 0x84000000 | 0xbfd7e | 0x84000000 | 0xbfd7f
1 | way 3 | set 48 | @ 0x6fc00 | 0x84000000 | 0xbfd80 | 0x84000000 | 0xbfd81 | 0x84000000 | 0xbfd82 | 0x84000000 | 0xbfd83 | 0x84000000 | 0xbfd84 | 0x84000000 | 0xbfd85 | 0x84000000 | 0xbfd86 | 0x84000000 | 0xbfd87
1 | way 3 | set 49 | @ 0xbac40 | 0x84000000 | 0xbfd88 | 0x84000000 | 0xbfd89 | 0x84000000 | 0xbfd8a | 0x84000000 | 0xbfd8b | 0x84000000 | 0xbfd8c | 0x84000000 | 0xbfd8d | 0x84000000 | 0xbfd8e | 0x84000000 | 0xbfd8f
1 | way 3 | set 50 | @ 0xbfc0dc80 | 0 | 0 | 0 | 0 | 0 | 0x1a8 | 0 | 0x800000 | 0xb0000 | 0 | 0x65646f63 | 0 | 0 | 0 | 0 | 0
1 | way 3 | set 51 | @ 0xbacc0 | 0x84000000 | 0xbfd98 | 0x84000000 | 0xbfd99 | 0x84000000 | 0xbfd9a | 0x84000000 | 0xbfd9b | 0x84000000 | 0xbfd9c | 0x84000000 | 0xbfd9d | 0x84000000 | 0xbfd9e | 0x84000000 | 0xbfd9f
1 | way 3 | set 52 | @ 0xbcd00 | 0x84000000 | 0xbffa0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 3 | set 53 | @ 0x94d40 | 0x84000000 | 0xbfda8 | 0x84000000 | 0xbfda9 | 0x84000000 | 0xbfdaa | 0x84000000 | 0xbfdab | 0x84000000 | 0xbfdac | 0x84000000 | 0xbfdad | 0x84000000 | 0xbfdae | 0x84000000 | 0xbfdaf
1 | way 3 | set 54 | @ 0x6fd80 | 0x84000000 | 0xbfdb0 | 0x84000000 | 0xbfdb1 | 0x84000000 | 0xbfdb2 | 0x84000000 | 0xbfdb3 | 0x84000000 | 0xbfdb4 | 0x84000000 | 0xbfdb5 | 0x84000000 | 0xbfdb6 | 0x84000000 | 0xbfdb7
1 | way 3 | set 55 | @ 0x94dc0 | 0x84000000 | 0xbfdb8 | 0x84000000 | 0xbfdb9 | 0x84000000 | 0xbfdba | 0x84000000 | 0xbfdbb | 0x84000000 | 0xbfdbc | 0x84000000 | 0xbfdbd | 0x84000000 | 0xbfdbe | 0x84000000 | 0xbfdbf
1 | way 3 | set 56 | @ 0x6fe00 | 0x84000000 | 0xbfdc0 | 0x84000000 | 0xbfdc1 | 0x84000000 | 0xbfdc2 | 0x84000000 | 0xbfdc3 | 0x84000000 | 0xbfdc4 | 0x84000000 | 0xbfdc5 | 0x84000000 | 0xbfdc6 | 0x84000000 | 0xbfdc7
1 | way 3 | set 57 | @ 0xbae40 | 0x84000000 | 0xbfdc8 | 0x84000000 | 0xbfdc9 | 0x84000000 | 0xbfdca | 0x84000000 | 0xbfdcb | 0x84000000 | 0xbfdcc | 0x84000000 | 0xbfdcd | 0x84000000 | 0xbfdce | 0x84000000 | 0xbfdcf
1 | way 3 | set 58 | @ 0x94e80 | 0x84000000 | 0xbfdd0 | 0x84000000 | 0xbfdd1 | 0x84000000 | 0xbfdd2 | 0x84000000 | 0xbfdd3 | 0x84000000 | 0xbfdd4 | 0x84000000 | 0xbfdd5 | 0x84000000 | 0xbfdd6 | 0x84000000 | 0xbfdd7
1 | way 3 | set 59 | @ 0x94ec0 | 0x84000000 | 0xbfdd8 | 0x84000000 | 0xbfdd9 | 0x84000000 | 0xbfdda | 0x84000000 | 0xbfddb | 0x84000000 | 0xbfddc | 0x84000000 | 0xbfddd | 0x84000000 | 0xbfdde | 0x84000000 | 0xbfddf
1 | way 3 | set 60 | @ 0xf00 | 0x1 | 0 | 0x101 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x3 | 0x10003 | 0x20003 | 0x30003 | 0x40003 | 0x50003
1 | way 3 | set 61 | @ 0xbfc0df40 | 0 | 0x2 | 0x3 | 0xffffffff | 0 | 0x1 | 0 | 0 | 0 | 0x6e69616d | 0 | 0 | 0 | 0 | 0 | 0
1 | way 3 | set 62 | @ 0xbdf80 | 0x84000000 | 0xff0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 3 | set 63 | @ 0x6ffc0 | 0x84000000 | 0xbfdf8 | 0x84000000 | 0xbfdf9 | 0x84000000 | 0xbfdfa | 0x84000000 | 0xbfdfb | 0x84000000 | 0xbfdfc | 0x84000000 | 0xbfdfd | 0x84000000 | 0xbfdfe | 0x84000000 | 0xbfdff
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_IDLE> Read request: srcid = 1 / address = 0xd000 / pktid = 0x3 / nwords = 16
****************** cycle 1701314 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0xac400000 PTE_PPN = 0xbfc0a
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
****************** cycle 1701315 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB: way = 0 / set = 2
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_LOCK> Accessing directory:  address = 0xd000 / hit = 1 / count = 2 / is_cnt = 0
****************** cycle 1701316 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB / set = 2 / way = 0
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
     [2] [0]   [1][1][0][1][1][0][0][0][1][0][1][0x17f81][  0xbfc0a][0x000000601]
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_REQ> Requesting HEAP lock 
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 3 / rdata = 0x27bdff98 / cpt = 0
****************** cycle 1701317 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_LOCK> Update directory: tag = 0x3 set = 64 way = 7 count = 3 is_cnt = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 3 / rdata = 0xafbf0064 / cpt = 1
****************** cycle 1701318 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_WRITE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x27bdff98 WAY = 0x1 SET = 0 WORD = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_WRITE> Add an entry in the heap: owner_id = 0x1 owner_ins = 0x1
****************** cycle 1701319 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_IDLE> Cache update in P1 stage / WAY = 0 / SET = 63 / WORD = 15 / DATA = 0xbfc00524 / BE = 0x0f
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xafbf0064 WAY = 0x1 SET = 0 WORD = 0x1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 3 / rdata = 0xafbe0060 / cpt = 2
****************** cycle 1701320 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_IDLE> Cache update in P1 stage / WAY = 0 / SET = 63 / WORD = 14 / DATA = 0 / BE = 0x0f
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xafbe0060 WAY = 0x1 SET = 0 WORD = 0x2
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 3 / rdata = 0x3a0f021 / cpt = 3
****************** cycle 1701321 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x3a0f021 WAY = 0x1 SET = 0 WORD = 0x3
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 3 / rdata = 0xc0001c3 / cpt = 4
****************** cycle 1701322 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xc0001c3 WAY = 0x1 SET = 0 WORD = 0x4
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 3 / rdata = 0 / cpt = 5
****************** cycle 1701323 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0 WAY = 0x1 SET = 0 WORD = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 3 / rdata = 0xafc2005c / cpt = 6
****************** cycle 1701324 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x8000070c / BYPASS = 0x1 / PTE_ADR = 0x000019000
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xafc2005c WAY = 0x1 SET = 0 WORD = 0x6
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 3 / rdata = 0x8fc2005c / cpt = 7
****************** cycle 1701325 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_TLB_PTE2_GET> MISS in dcache: PTE address = 0x000019000
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x8fc2005c WAY = 0x1 SET = 0 WORD = 0x7
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 3 / rdata = 0x21082 / cpt = 8
****************** cycle 1701326 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_MISS_SELECT> Select a slot: / WAY = 2 / SET = 0 / PADDR = 0x000019000 / VICTIM = 0x000002e80
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x21082 WAY = 0x1 SET = 0 WORD = 0x8
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 3 / rdata = 0xafc20058 / cpt = 9
****************** cycle 1701327 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_MISS_CLEAN> Switch to ZOMBI state / way = 2 / set = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 2948726872 WAY = 1 SET = 0 WORD = 9
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 3 / rdata = 0x8fc2005c / cpt = 10
****************** cycle 1701328 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_dcache_cc_send_nline = 0x000002e80
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x8fc2005c WAY = 0x1 SET = 0 WORD = 0xa
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d0 / for address 0x000019000
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 3 / rdata = 0x30420003 / cpt = 11
****************** cycle 1701329 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_READ | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_dcache_cc_send_nline = 0x000002e80
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x30420003 WAY = 0x1 SET = 0 WORD = 0xb
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_READ> Push into read_fifo: address = 0x000019000 srcid = 0d0 trdid = 0d0 pktid = 0d1 plen = 0d64
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 3 / rdata = 0xc0004f1 / cpt = 12
****************** cycle 1701330 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xc0004f1 WAY = 0x1 SET = 0 WORD = 0xc
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 3 / rdata = 0xafc20054 / cpt = 13
****************** cycle 1701331 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_CLEANUP | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xafc20054 WAY = 0x1 SET = 0 WORD = 0xd
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 3 / rdata = 0xc000342 / cpt = 14
****************** cycle 1701332 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_CLEANUP | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xc000342 WAY = 0x1 SET = 0 WORD = 0xe
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CLEANUP_IDLE> Cleanup request: / owner_id = 0 / owner_ins = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 3 / rdata = 0xafc20050 / cpt = 15
****************** cycle 1701333 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_GET_NLINE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xafc20050 WAY = 0x1 SET = 0 WORD = 0xf
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_RSP> Request the TGT_RSP FSM to return data: rsrcid = 1 / address = 0xd000 / nwords = 16
  <MEMC memc_0_0.CLEANUP_GET_NLINE> Cleanup request: / address = 0xba000
****************** cycle 1701334 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 ICACHE_MISS_DIR_UPDT> Switch cache slot to VALID state PADDR = 0x00000d000 WAY = 1 SET = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_IDLE> Read request: srcid = 2 / address = 0xd000 / pktid = 0x3 / nwords = 16
****************** cycle 1701335 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.CLEANUP_DIR_REQ> Requesting DIR lock 
****************** cycle 1701336 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_DIR_LOCK
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.CLEANUP_DIR_LOCK> Test directory status:  line = 0x000000ba000 / hit = 0x1 / dir_id = 0 / dir_ins = 0 / search_id = 0 / search_ins = 0 / count = 0x1 / is_cnt = 0
****************** cycle 1701337 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_DIR_WRITE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.CLEANUP_DIR_WRITE> Update directory: address = 0xba000 / dir_id = 0 / dir_ins = 0 / count = 0 / is_cnt = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 3 / rdata = 0x27bdff98 / cpt = 0
****************** cycle 1701338 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_SEND_ACK
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> DTLB miss / VADDR = 0xbfc0b3fc / BYPASS = 0 / PTE_ADR = 0x0000137f8
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.CLEANUP_SEND_ACK> Send the response to a cleanup request: srcid = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 3 / rdata = 0xafbf0064 / cpt = 1
****************** cycle 1701339 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x27bdff98 WAY = 0x1 SET = 0 WORD = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE1_GET> HIT in dcache / paddr = 0x0000137f8 / way = 0 / set = 31 / word = 14 / PTD = 0xc0000018
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_LOCK> Accessing directory:  address = 0xd000 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1701340 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_ACK | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xafbf0064 WAY = 0x1 SET = 0 WORD = 0x1
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_GET> MISS in dcache: PTE address = 0x000018058
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_REQ> Requesting HEAP lock 
  <MEMC memc_0_0.CC_SEND_CLEANUP_ACK> Cleanup Acknowledgement for srcid 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 3 / rdata = 0xafbe0060 / cpt = 2
****************** cycle 1701341 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xafbe0060 WAY = 0x1 SET = 0 WORD = 0x2
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_SELECT> Select a slot: / WAY = 0 / SET = 1 / PADDR = 0x000018058
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_LOCK> Update directory: tag = 0x3 set = 64 way = 7 count = 4 is_cnt = 1
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 3 / rdata = 0x3a0f021 / cpt = 3
****************** cycle 1701342 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_ERASE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x3a0f021 WAY = 0x1 SET = 0 WORD = 0x3
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 3 / rdata = 0xc0001c3 / cpt = 4
****************** cycle 1701343 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_LAST | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xc0001c3 WAY = 0x1 SET = 0 WORD = 0x4
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000018040
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 3 / rdata = 0 / cpt = 5
****************** cycle 1701344 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_READ | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0 WAY = 0x1 SET = 0 WORD = 0x5
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_READ> Push into read_fifo: address = 0x000018040 srcid = 0d3 trdid = 0d0 pktid = 0d1 plen = 0d64
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 3 / rdata = 0xafc2005c / cpt = 6
****************** cycle 1701345 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_CC_CHECK> paddr = 0x000019480 r_dcache_vci_paddr = 0x000019000 mask = 0x0ffffffc0 (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) = 0x1 (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT) = 0 ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) = 0
  <PROC proc_0_0_0 DCACHE_CC_CHECK> CC_TYPE_CLACK Switch slot to EMPTY state set = 0 / way = 0x2
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xafc2005c WAY = 0x1 SET = 0 WORD = 0x6
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 3 / rdata = 0x8fc2005c / cpt = 7
****************** cycle 1701346 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x8fc2005c WAY = 0x1 SET = 0 WORD = 0x7
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 3 / rdata = 0x21082 / cpt = 8
****************** cycle 1701347 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x21082 WAY = 0x1 SET = 0 WORD = 0x8
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 3 / rdata = 0xafc20058 / cpt = 9
****************** cycle 1701348 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xafc20058 WAY = 0x1 SET = 0 WORD = 0x9
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 3 / rdata = 0x8fc2005c / cpt = 10
****************** cycle 1701349 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x8fc2005c WAY = 0x1 SET = 0 WORD = 0xa
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 3 / rdata = 0x30420003 / cpt = 11
****************** cycle 1701350 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x30420003 WAY = 0x1 SET = 0 WORD = 0xb
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 3 / rdata = 0xc0004f1 / cpt = 12
****************** cycle 1701351 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xc0004f1 WAY = 0x1 SET = 0 WORD = 0xc
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 3 / rdata = 0xafc20054 / cpt = 13
****************** cycle 1701352 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xafc20054 WAY = 0x1 SET = 0 WORD = 0xd
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 3 / rdata = 0xc000342 / cpt = 14
****************** cycle 1701353 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xc000342 WAY = 0x1 SET = 0 WORD = 0xe
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 3 / rdata = 0xafc20050 / cpt = 15
****************** cycle 1701354 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xafc20050 WAY = 0x1 SET = 0 WORD = 0xf
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_RSP> Request the TGT_RSP FSM to return data: rsrcid = 2 / address = 0xd000 / nwords = 16
****************** cycle 1701355 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 ICACHE_MISS_DIR_UPDT> Switch cache slot to VALID state PADDR = 0x00000d000 WAY = 1 SET = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_IDLE> Read request: srcid = 0 / address = 0x19000 / pktid = 0x1 / nwords = 16
****************** cycle 1701356 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
****************** cycle 1701357 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_LOCK> Accessing directory:  address = 0x19000 / hit = 1 / count = 0 / is_cnt = 0
****************** cycle 1701358 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_HIT | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_HIT> Update directory entry: addr = 0x19000 / set = 64 / way = 1 / owner_id = 0 / owner_ins = 0 / count = 1 / is_cnt = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 3 / rdata = 0x27bdff98 / cpt = 0
****************** cycle 1701359 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1.DCACHE_TLB_MISS> DTLB miss / VADDR = 0xbfc0b1fc / BYPASS = 0 / PTE_ADR = 0x0000137f8
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 3 / rdata = 0xafbf0064 / cpt = 1
****************** cycle 1701360 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_DATA_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1.DCACHE_TLB_PTE1_GET> HIT in dcache / paddr = 0x0000137f8 / way = 0 / set = 31 / word = 14 / PTD = 0xc0000018
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x27bdff98 WAY = 0x1 SET = 0 WORD = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701361 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_DATA_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_TLB_PTE2_GET> MISS in dcache: PTE address = 0x000018058
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xafbf0064 WAY = 0x1 SET = 0 WORD = 0x1
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 3 / rdata = 0xafbe0060 / cpt = 2
****************** cycle 1701362 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_DATA_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_SELECT> Select a slot: / WAY = 0 / SET = 1 / PADDR = 0x000018058
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xafbe0060 WAY = 0x1 SET = 0 WORD = 0x2
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 3 / rdata = 0x3a0f021 / cpt = 3
****************** cycle 1701363 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_DATA_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x3a0f021 WAY = 0x1 SET = 0 WORD = 0x3
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 3 / rdata = 0xc0001c3 / cpt = 4
****************** cycle 1701364 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_DATA_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xc0001c3 WAY = 0x1 SET = 0 WORD = 0x4
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d1 / for address 0x000018040
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 3 / rdata = 0 / cpt = 5
****************** cycle 1701365 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_DATA_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_READ | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0 WAY = 0x1 SET = 0 WORD = 0x5
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_READ> Push into read_fifo: address = 0x000018040 srcid = 0d1 trdid = 0d0 pktid = 0d1 plen = 0d64
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 3 / rdata = 0xafc2005c / cpt = 6
****************** cycle 1701366 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_DATA_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xafc2005c WAY = 0x1 SET = 0 WORD = 0x6
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 3 / rdata = 0x8fc2005c / cpt = 7
****************** cycle 1701367 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_DATA_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x8fc2005c WAY = 0x1 SET = 0 WORD = 0x7
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 3 / rdata = 0x21082 / cpt = 8
****************** cycle 1701368 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_DATA_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x21082 WAY = 0x1 SET = 0 WORD = 0x8
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 3 / rdata = 0xafc20058 / cpt = 9
****************** cycle 1701369 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_DATA_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xafc20058 WAY = 0x1 SET = 0 WORD = 0x9
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 3 / rdata = 0x8fc2005c / cpt = 10
****************** cycle 1701370 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_DATA_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x8fc2005c WAY = 0x1 SET = 0 WORD = 0xa
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 3 / rdata = 0x30420003 / cpt = 11
****************** cycle 1701371 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_DATA_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x30420003 WAY = 0x1 SET = 0 WORD = 0xb
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 3 / rdata = 0xc0004f1 / cpt = 12
****************** cycle 1701372 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_DATA_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xc0004f1 WAY = 0x1 SET = 0 WORD = 0xc
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 3 / rdata = 0xafc20054 / cpt = 13
****************** cycle 1701373 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_DATA_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xafc20054 WAY = 0x1 SET = 0 WORD = 0xd
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 3 / rdata = 0xc000342 / cpt = 14
****************** cycle 1701374 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_DATA_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xc000342 WAY = 0x1 SET = 0 WORD = 0xe
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 3 / rdata = 0xafc20050 / cpt = 15
****************** cycle 1701375 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_DATA_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xafc20050 WAY = 0x1 SET = 0 WORD = 0xf
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_RSP> Request the TGT_RSP FSM to return data: rsrcid = 0 / address = 0x19000 / nwords = 16
****************** cycle 1701376 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_MISS_DIR_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 ICACHE_MISS_DIR_UPDT> Switch cache slot to VALID state PADDR = 0x00000d000 WAY = 1 SET = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_IDLE> Read request: srcid = 3 / address = 0x18040 / pktid = 0x1 / nwords = 16
****************** cycle 1701377 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp  invalid no error ins 0>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
****************** cycle 1701378 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090000>
  <InsRsp    valid no error ins 0x27bdff98>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_LOCK> Accessing directory:  address = 0x18040 / hit = 1 / count = 1 / is_cnt = 0
****************** cycle 1701379 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090004>
  <InsRsp    valid no error ins 0xafbf0064>
  <DataReq invalid mode MODE_KERNEL type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_REQ> Requesting HEAP lock 
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0x8a000000 / cpt = 0
****************** cycle 1701380 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_MISS | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2.DCACHE_TLB_MISS> DTLB miss / VADDR = 0xbfc0b2fc / BYPASS = 0 / PTE_ADR = 0x0000137f8
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_LOCK> Update directory: tag = 0x6 set = 1 way = 0 count = 2 is_cnt = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0x4 / cpt = 1
****************** cycle 1701381 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE1_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_WRITE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x8a000000 / WAY = 2 / SET = 0 / WORD = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2.DCACHE_TLB_PTE1_GET> HIT in dcache / paddr = 0x0000137f8 / way = 0 / set = 31 / word = 14 / PTD = 0xc0000018
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_WRITE> Add an entry in the heap: owner_id = 0x3 owner_ins = 0
****************** cycle 1701382 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x4 / WAY = 2 / SET = 0 / WORD = 1
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_TLB_PTE2_GET> MISS in dcache: PTE address = 0x000018058
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0x8a000000 / cpt = 2
****************** cycle 1701383 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_SELECT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x8a000000 / WAY = 2 / SET = 0 / WORD = 2
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_SELECT> Select a slot: / WAY = 0 / SET = 1 / PADDR = 0x000018058
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0x5 / cpt = 3
****************** cycle 1701384 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_DATA_MISS | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x5 / WAY = 2 / SET = 0 / WORD = 3
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0x8a000000 / cpt = 4
****************** cycle 1701385 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_DATA_MISS | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x8a000000 / WAY = 2 / SET = 0 / WORD = 4
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d2 / for address 0x000018040
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0x6 / cpt = 5
****************** cycle 1701386 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_DATA_MISS | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_READ | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x6 / WAY = 2 / SET = 0 / WORD = 5
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_READ> Push into read_fifo: address = 0x000018040 srcid = 0d2 trdid = 0d0 pktid = 0d1 plen = 0d64
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0x8a000000 / cpt = 6
****************** cycle 1701387 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x8a000000 / WAY = 2 / SET = 0 / WORD = 6
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0x7 / cpt = 7
****************** cycle 1701388 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x7 / WAY = 2 / SET = 0 / WORD = 7
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 8
****************** cycle 1701389 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 8
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 9
****************** cycle 1701390 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 9
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 10
****************** cycle 1701391 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 10
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 11
****************** cycle 1701392 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 11
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 12
****************** cycle 1701393 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 12
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 13
****************** cycle 1701394 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 13
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 14
****************** cycle 1701395 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 14
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 15
****************** cycle 1701396 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 0 / WORD = 15
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_RSP> Request the TGT_RSP FSM to return data: rsrcid = 3 / address = 0x18040 / nwords = 16
****************** cycle 1701397 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DIR_UPDT> Switch slot to VALID state PADDR = 0x000019000 / WAY = 2 / SET = 0
1 | way 0 | set 0 | @ 0x13000 | 0xc0000019 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 1 | @ 0x94040 | 0x8c000000 | 0xbfc08 | 0x8c000000 | 0xbfc09 | 0xac400000 | 0xbfc0a | 0x8c000000 | 0xbfc0b | 0xac000000 | 0xbfc0c | 0xac000000 | 0xbfc0d | 0x8c000000 | 0xbfc0e | 0 | 0
1 | way 0 | set 2 | @ 0xbfc0c080 | 0 | 0x6 | 0 | 0x47455350 | 0x4d41525f | 0 | 0 | 0 | 0 | 0 | 0x75000000 | 0 | 0xc00000 | 0 | 0 | 0xd6000
1 | way 0 | set 3 | @ 0xbfc0e0c0 | 0x12 | 0x2 | 0x2 | 0 | 0x13 | 0x2 | 0x3 | 0 | 0x14 | 0x2 | 0x4 | 0 | 0x15 | 0x2 | 0x5 | 0
1 | way 0 | set 4 | @ 0xbfc0e100 | 0x16 | 0x2 | 0x6 | 0 | 0x17 | 0x2 | 0x7 | 0 | 0x18 | 0x2 | 0x8 | 0 | 0x19 | 0x2 | 0x9 | 0
1 | way 0 | set 5 | @ 0xbfc0c140 | 0 | 0 | 0xf00000 | 0x1000 | 0x2 | 0 | 0xf00000 | 0x47455350 | 0x434f495f | 0 | 0 | 0 | 0 | 0 | 0 | 0xbff10000
1 | way 0 | set 6 | @ 0xbfc0e180 | 0x1e | 0x2 | 0xe | 0 | 0x1f | 0x4 | 0 | 0x1 | 0x1 | 0x1 | 0 | 0x1 | 0x2 | 0x1 | 0 | 0x1
1 | way 0 | set 7 | @ 0xbc1c0 | 0x84000000 | 0xbfe38 | 0x84000000 | 0xbfe39 | 0x84000000 | 0xbfe3a | 0x84000000 | 0xbfe3b | 0x84000000 | 0xbfe3c | 0x84000000 | 0xbfe3d | 0x84000000 | 0xbfe3e | 0x84000000 | 0xbfe3f
1 | way 0 | set 8 | @ 0xbfc0c200 | 0 | 0 | 0 | 0 | 0 | 0 | 0xbff80000 | 0x21000 | 0x2 | 0 | 0xbff80000 | 0x47455350 | 0x4443475f | 0 | 0 | 0
1 | way 0 | set 9 | @ 0x6e240 | 0x84000000 | 0xbfe48 | 0x84000000 | 0xbfe49 | 0x84000000 | 0xbfe4a | 0x84000000 | 0xbfe4b | 0x84000000 | 0xbfe4c | 0x84000000 | 0xbfe4d | 0x84000000 | 0xbfe4e | 0x84000000 | 0xbfe4f
1 | way 0 | set 10 | @ 0x6e280 | 0x84000000 | 0xbfe50 | 0x84000000 | 0xbfe51 | 0x84000000 | 0xbfe52 | 0x84000000 | 0xbfe53 | 0x84000000 | 0xbfe54 | 0x84000000 | 0xbfe55 | 0x84000000 | 0xbfe56 | 0x84000000 | 0xbfe57
1 | way 0 | set 11 | @ 0x962c0 | 0x84000000 | 0xbfe58 | 0x84000000 | 0xbfe59 | 0x84000000 | 0xbfe5a | 0x84000000 | 0xbfe5b | 0x84000000 | 0xbfe5c | 0x84000000 | 0xbfe5d | 0x84000000 | 0xbfe5e | 0x84000000 | 0xbfe5f
1 | way 0 | set 12 | @ 0x96300 | 0x84000000 | 0xbfe60 | 0x84000000 | 0xbfe61 | 0x84000000 | 0xbfe62 | 0x84000000 | 0xbfe63 | 0x84000000 | 0xbfe64 | 0x84000000 | 0xbfe65 | 0x84000000 | 0xbfe66 | 0x84000000 | 0xbfe67
1 | way 0 | set 13 | @ 0xbc340 | 0x84000000 | 0xbfe68 | 0x84000000 | 0xbfe69 | 0x84000000 | 0xbfe6a | 0x84000000 | 0xbfe6b | 0x84000000 | 0xbfe6c | 0x84000000 | 0xbfe6d | 0x84000000 | 0xbfe6e | 0x84000000 | 0xbfe6f
1 | way 0 | set 14 | @ 0x96380 | 0x84000000 | 0xbfe70 | 0x84000000 | 0xbfe71 | 0x84000000 | 0xbfe72 | 0x84000000 | 0xbfe73 | 0x84000000 | 0xbfe74 | 0x84000000 | 0xbfe75 | 0x84000000 | 0xbfe76 | 0x84000000 | 0xbfe77
1 | way 0 | set 15 | @ 0xbfc043c0 | 0xff0106d | 0 | 0x3c0e821 | 0x8fbf0014 | 0x8fbe0010 | 0x27bd0018 | 0x3e00008 | 0 | 0x33323130 | 0x37363534 | 0x42413938 | 0x46454443 | 0 | 0x33323130 | 0x37363534 | 0x3938
1 | way 0 | set 16 | @ 0xbfc0d400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x2fc | 0 | 0x800000 | 0xe000 | 0 | 0x65646f63 | 0
1 | way 0 | set 17 | @ 0xbfc04440 | 0x6974636e | 0x62206e6f | 0x5f746f6f | 0x67657370 | 0x7465675f | 0xa2928 | 0x6f666e55 | 0x20646e75 | 0x65676170 | 0x62617420 | 0x6620656c | 0x7620726f | 0x63617073 | 0x2065 | 0xa | 0x4f425b0a
1 | way 0 | set 18 | @ 0xbfc0d480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x240c | 0 | 0x400000 | 0xf000 | 0 | 0x62617470 | 0 | 0 | 0
1 | way 0 | set 19 | @ 0xbfc0c4c0 | 0x645f6c65 | 0x617461 | 0 | 0 | 0 | 0 | 0x80010000 | 0x8000 | 0x4000 | 0 | 0xa | 0 | 0x1 | 0x4 | 0x5f676573 | 0x6e72656b
1 | way 0 | set 20 | @ 0xbfc0d500 | 0 | 0 | 0 | 0 | 0x2 | 0x12000 | 0xd | 0x300000 | 0x12000 | 0 | 0x63617473 | 0x705f6b | 0 | 0 | 0 | 0
1 | way 0 | set 21 | @ 0xbfc0c540 | 0x695f6c65 | 0x74696e | 0 | 0 | 0 | 0 | 0x80090000 | 0xd000 | 0x1000 | 0 | 0xc | 0 | 0x1 | 0x6 | 0x5f676573 | 0x666266
1 | way 0 | set 22 | @ 0xbfc0d580 | 0 | 0 | 0x6 | 0x10000 | 0 | 0x10000 | 0x24000 | 0 | 0x63617473 | 0x635f6b | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 23 | @ 0xbfc0c5c0 | 0 | 0 | 0 | 0 | 0 | 0x20000000 | 0xf00000 | 0xf00000 | 0x1000 | 0x3 | 0x2 | 0x1 | 0x1 | 0x8 | 0x5f676573 | 0x636f69
1 | way 0 | set 24 | @ 0xbfc0c600 | 0 | 0 | 0 | 0 | 0 | 0 | 0xbff10000 | 0xbff10000 | 0x1000 | 0x4 | 0x2 | 0x1 | 0x1 | 0x9 | 0x5f676573 | 0x797474
1 | way 0 | set 25 | @ 0xbfc0c640 | 0 | 0 | 0 | 0 | 0 | 0 | 0xbff20000 | 0xbff20000 | 0x1000 | 0x5 | 0x2 | 0x1 | 0x1 | 0xa | 0x5f676573 | 0x616d64
1 | way 0 | set 26 | @ 0xbfc0c680 | 0 | 0 | 0 | 0 | 0 | 0 | 0xf30000 | 0xf30000 | 0x1000 | 0x6 | 0x2 | 0x1 | 0x1 | 0xb | 0x5f676573 | 0x646367
1 | way 0 | set 27 | @ 0xbfc0c6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xf50000 | 0xf50000 | 0x1000 | 0x8 | 0x2 | 0x1 | 0x1 | 0xc | 0x5f676573 | 0x626f69
1 | way 0 | set 28 | @ 0xbfc0c700 | 0 | 0 | 0 | 0 | 0 | 0 | 0xff0000 | 0xff0000 | 0x1000 | 0xa | 0x2 | 0x1 | 0x1 | 0xd | 0x5f676573 | 0x63696e
1 | way 0 | set 29 | @ 0xbfc0c740 | 0 | 0 | 0 | 0 | 0 | 0 | 0xbffa0000 | 0xbffa0000 | 0x1000 | 0x7 | 0x2 | 0x1 | 0x1 | 0xe | 0x5f676573 | 0x61746164
1 | way 0 | set 30 | @ 0xbc780 | 0x84000000 | 0xbfef0 | 0x84000000 | 0xbfef1 | 0x84000000 | 0xbfef2 | 0x84000000 | 0xbfef3 | 0x84000000 | 0xbfef4 | 0x84000000 | 0xbfef5 | 0x84000000 | 0xbfef6 | 0x84000000 | 0xbfef7
1 | way 0 | set 31 | @ 0x697c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xc000006f | 0xc000006e
1 | way 0 | set 32 | @ 0xb8800 | 0x88000000 | 0xb4 | 0x88000000 | 0xb5 | 0x88000000 | 0xb6 | 0x88000000 | 0xb7 | 0x88000000 | 0xb8 | 0x88000000 | 0xb9 | 0x88000000 | 0xba | 0x88000000 | 0xbb
1 | way 0 | set 33 | @ 0xbfc0d840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x94 | 0 | 0x800000 | 0x65000 | 0 | 0x65646f63 | 0 | 0 | 0
1 | way 0 | set 34 | @ 0xb8880 | 0x88000000 | 0xc4 | 0x88000000 | 0xc5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 35 | @ 0x948c0 | 0x84000000 | 0xbfd18 | 0x84000000 | 0xbfd19 | 0x84000000 | 0xbfd1a | 0x84000000 | 0xbfd1b | 0x84000000 | 0xbfd1c | 0x84000000 | 0xbfd1d | 0x84000000 | 0xbfd1e | 0x84000000 | 0xbfd1f
1 | way 0 | set 36 | @ 0xba900 | 0x84000000 | 0xbfd20 | 0x84000000 | 0xbfd21 | 0x84000000 | 0xbfd22 | 0x84000000 | 0xbfd23 | 0x84000000 | 0xbfd24 | 0x84000000 | 0xbfd25 | 0x84000000 | 0xbfd26 | 0x84000000 | 0xbfd27
1 | way 0 | set 37 | @ 0xbfc0d940 | 0 | 0 | 0x2 | 0x12000 | 0xd | 0x300000 | 0x68000 | 0 | 0x63617473 | 0x6b | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 38 | @ 0xba980 | 0x84000000 | 0xbfd30 | 0x84000000 | 0xbfd31 | 0x84000000 | 0xbfd32 | 0x84000000 | 0xbfd33 | 0x84000000 | 0xbfd34 | 0x84000000 | 0xbfd35 | 0x84000000 | 0xbfd36 | 0x84000000 | 0xbfd37
1 | way 0 | set 39 | @ 0x949c0 | 0x84000000 | 0xbfd38 | 0x84000000 | 0xbfd39 | 0x84000000 | 0xbfd3a | 0x84000000 | 0xbfd3b | 0x84000000 | 0xbfd3c | 0x84000000 | 0xbfd3d | 0x84000000 | 0xbfd3e | 0x84000000 | 0xbfd3f
1 | way 0 | set 40 | @ 0x94a00 | 0x84000000 | 0xbfd40 | 0x84000000 | 0xbfd41 | 0x84000000 | 0xbfd42 | 0x84000000 | 0xbfd43 | 0x84000000 | 0xbfd44 | 0x84000000 | 0xbfd45 | 0x84000000 | 0xbfd46 | 0x84000000 | 0xbfd47
1 | way 0 | set 41 | @ 0x94a40 | 0x84000000 | 0xbfd48 | 0x84000000 | 0xbfd49 | 0x84000000 | 0xbfd4a | 0x84000000 | 0xbfd4b | 0x84000000 | 0xbfd4c | 0x84000000 | 0xbfd4d | 0x84000000 | 0xbfd4e | 0x84000000 | 0xbfd4f
1 | way 0 | set 42 | @ 0xbda80 | 0x84000000 | 0xf50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 43 | @ 0xbaac0 | 0x84000000 | 0xbfd58 | 0x84000000 | 0xbfd59 | 0x84000000 | 0xbfd5a | 0x84000000 | 0xbfd5b | 0x84000000 | 0xbfd5c | 0x84000000 | 0xbfd5d | 0x84000000 | 0xbfd5e | 0x84000000 | 0xbfd5f
1 | way 0 | set 44 | @ 0xbab00 | 0x84000000 | 0xbfd60 | 0x84000000 | 0xbfd61 | 0x84000000 | 0xbfd62 | 0x84000000 | 0xbfd63 | 0x84000000 | 0xbfd64 | 0x84000000 | 0xbfd65 | 0x84000000 | 0xbfd66 | 0x84000000 | 0xbfd67
1 | way 0 | set 45 | @ 0xbfc04b40 | 0x7461636f | 0x2073726f | 0x74696e69 | 0x696c6169 | 0x69746173 | 0x63206e6f | 0x6c706d6f | 0x64657465 | 0x20746120 | 0x6c637963 | 0x2065 | 0x4f425b0a | 0x205d544f | 0x65676150 | 0x62615420 | 0x2073656c
1 | way 0 | set 46 | @ 0xbfc04b80 | 0x74696e69 | 0x696c6169 | 0x69746173 | 0x63206e6f | 0x6c706d6f | 0x64657465 | 0x20746120 | 0x6c637963 | 0x2065 | 0x4f425b0a | 0x205d544f | 0x6a626f56 | 0x6e692073 | 0x61697469 | 0x6173696c | 0x6e6f6974
1 | way 0 | set 47 | @ 0xbfc0cbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x800000 | 0xb0000 | 0x1000 | 0 | 0xb | 0 | 0x1 | 0x21 | 0x5f676573 | 0x65646f63
1 | way 0 | set 48 | @ 0xbfc0dc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0x6 | 0x10000 | 0 | 0x10000 | 0xa0000 | 0 | 0x61746164 | 0 | 0 | 0
1 | way 0 | set 49 | @ 0xbfc0cc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0x300000 | 0xb4000 | 0x12000 | 0 | 0x8 | 0 | 0x1 | 0x23 | 0x5f676573 | 0x63617473
1 | way 0 | set 50 | @ 0xbac80 | 0x84000000 | 0xbfd90 | 0x84000000 | 0xbfd91 | 0x84000000 | 0xbfd92 | 0x84000000 | 0xbfd93 | 0x84000000 | 0xbfd94 | 0x84000000 | 0xbfd95 | 0x84000000 | 0xbfd96 | 0x84000000 | 0xbfd97
1 | way 0 | set 51 | @ 0x18cc0 | 0x84000000 | 0xbfd98 | 0x84000000 | 0xbfd99 | 0x84000000 | 0xbfd9a | 0x84000000 | 0xbfd9b | 0x84000000 | 0xbfd9c | 0x84000000 | 0xbfd9d | 0x84000000 | 0xbfd9e | 0x84000000 | 0xbfd9f
1 | way 0 | set 52 | @ 0xbfc0dd00 | 0 | 0 | 0 | 0x1714 | 0 | 0x400000 | 0xb1000 | 0 | 0x62617470 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 53 | @ 0xbfc04d40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x10 | 0x10 | 0x10
1 | way 0 | set 54 | @ 0xbfc0dd80 | 0x2 | 0x12000 | 0xd | 0x300000 | 0xb4000 | 0 | 0x63617473 | 0x6b | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 55 | @ 0xbadc0 | 0x84000000 | 0xbfdb8 | 0x84000000 | 0xbfdb9 | 0x84000000 | 0xbfdba | 0x84000000 | 0xbfdbb | 0x84000000 | 0xbfdbc | 0x84000000 | 0xbfdbd | 0x84000000 | 0xbfdbe | 0x84000000 | 0xbfdbf
1 | way 0 | set 56 | @ 0x94e00 | 0x84000000 | 0xbfdc0 | 0x84000000 | 0xbfdc1 | 0x84000000 | 0xbfdc2 | 0x84000000 | 0xbfdc3 | 0x84000000 | 0xbfdc4 | 0x84000000 | 0xbfdc5 | 0x84000000 | 0xbfdc6 | 0x84000000 | 0xbfdc7
1 | way 0 | set 57 | @ 0xbfc04e40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x300000 | 0x300000 | 0x300000
1 | way 0 | set 58 | @ 0xbae80 | 0x84000000 | 0xbfdd0 | 0x84000000 | 0xbfdd1 | 0x84000000 | 0xbfdd2 | 0x84000000 | 0xbfdd3 | 0x84000000 | 0xbfdd4 | 0x84000000 | 0xbfdd5 | 0x84000000 | 0xbfdd6 | 0x84000000 | 0xbfdd7
1 | way 0 | set 59 | @ 0xbaec0 | 0x84000000 | 0xbfdd8 | 0x84000000 | 0xbfdd9 | 0x84000000 | 0xbfdda | 0x84000000 | 0xbfddb | 0x84000000 | 0xbfddc | 0x84000000 | 0xbfddd | 0x84000000 | 0xbfdde | 0x84000000 | 0xbfddf
1 | way 0 | set 60 | @ 0x3f00 | 0x2 | 0 | 0 | 0 | 0 | 0x101 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 61 | @ 0xbfc0af40 | 0x400000 | 0x800000 | 0xbfc0dc30 | 0 | 0xffffffff | 0xffffffff | 0x7 | 0x300000 | 0 | 0x5a | 0xff13 | 0xbfc0067c | 0x101 | 0 | 0x1 | 0x3
1 | way 0 | set 62 | @ 0xbfc0af80 | 0x1 | 0x20 | 0x4 | 0 | 0x1 | 0x7 | 0x4 | 0 | 0x7 | 0xbff20000 | 0x1 | 0xbfc0afb0 | 0xbfc0afcb | 0xbfc0e00c | 0xbfc0dfec | 0xbfc0ccb8
1 | way 0 | set 63 | @ 0xbfc0afc0 | 0x3 | 0x7 | 0x31c0c08c | 0x35373936 | 0xbf003136 | 0x1 | 0xbfc0c000 | 0xbff20000 | 0xbfc0afe8 | 0xbfc0afe8 | 0xbfc04478 | 0 | 0 | 0 | 0 | 0xbfc00524
1 | way 1 | set 0 | @ 0x18000 | 0xae000000 | 0xbfc00 | 0x8e000000 | 0xbfc01 | 0x8e000000 | 0xbfc02 | 0xae000000 | 0xbfc03 | 0xae400000 | 0xbfc04 | 0x8e000000 | 0xbfc05 | 0 | 0 | 0 | 0
1 | way 1 | set 1 | @ 0xba040 | 0x8c000000 | 0xbfc08 | 0x8c000000 | 0xbfc09 | 0xac400000 | 0xbfc0a | 0x8c000000 | 0xbfc0b | 0xac400000 | 0xbfc0c | 0xac000000 | 0xbfc0d | 0x8c000000 | 0xbfc0e | 0 | 0
1 | way 1 | set 2 | @ 0xbfc0e080 | 0xe | 0x3 | 0x6 | 0 | 0xf | 0x3 | 0x7 | 0 | 0x10 | 0x2 | 0 | 0 | 0x11 | 0x2 | 0x1 | 0
1 | way 1 | set 3 | @ 0xb90c0 | 0x8d000000 | 0xce | 0x8d000000 | 0xcf | 0x8d000000 | 0xd0 | 0x8d000000 | 0xd1 | 0x8d000000 | 0xd2 | 0x8d000000 | 0xd3 | 0x8d000000 | 0xd4 | 0x8d000000 | 0xd5
1 | way 1 | set 4 | @ 0xbc100 | 0x84000000 | 0xbfe20 | 0x84000000 | 0xbfe21 | 0x84000000 | 0xbfe22 | 0x84000000 | 0xbfe23 | 0x84000000 | 0xbfe24 | 0x84000000 | 0xbfe25 | 0x84000000 | 0xbfe26 | 0x84000000 | 0xbfe27
1 | way 1 | set 5 | @ 0xbfc0e140 | 0x1a | 0x2 | 0xa | 0 | 0x1b | 0x2 | 0xb | 0 | 0x1c | 0x2 | 0xc | 0 | 0x1d | 0x2 | 0xd | 0
1 | way 1 | set 6 | @ 0xbc180 | 0x84000000 | 0xbfe30 | 0x84000000 | 0xbfe31 | 0x84000000 | 0xbfe32 | 0x84000000 | 0xbfe33 | 0x84000000 | 0xbfe34 | 0x84000000 | 0xbfe35 | 0x84000000 | 0xbfe36 | 0x84000000 | 0xbfe37
1 | way 1 | set 7 | @ 0xbfc0e1c0 | 0x3 | 0x1 | 0 | 0x4 | 0x4 | 0x1 | 0x7 | 0x7 | 0x8 | 0x5 | 0x5 | 0x8 | 0x3 | 0x6 | 0x1 | 0x2
1 | way 1 | set 8 | @ 0xbfc0e200 | 0x3 | 0x5 | 0x6 | 0x2 | 0x1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 9 | @ 0x96240 | 0x84000000 | 0xbfe48 | 0x84000000 | 0xbfe49 | 0x84000000 | 0xbfe4a | 0x84000000 | 0xbfe4b | 0x84000000 | 0xbfe4c | 0x84000000 | 0xbfe4d | 0x84000000 | 0xbfe4e | 0x84000000 | 0xbfe4f
1 | way 1 | set 10 | @ 0x96280 | 0x84000000 | 0xbfe50 | 0x84000000 | 0xbfe51 | 0x84000000 | 0xbfe52 | 0x84000000 | 0xbfe53 | 0x84000000 | 0xbfe54 | 0x84000000 | 0xbfe55 | 0x84000000 | 0xbfe56 | 0x84000000 | 0xbfe57
1 | way 1 | set 11 | @ 0xbc2c0 | 0x84000000 | 0xbfe58 | 0x84000000 | 0xbfe59 | 0x84000000 | 0xbfe5a | 0x84000000 | 0xbfe5b | 0x84000000 | 0xbfe5c | 0x84000000 | 0xbfe5d | 0x84000000 | 0xbfe5e | 0x84000000 | 0xbfe5f
1 | way 1 | set 12 | @ 0xbc300 | 0x84000000 | 0xbfe60 | 0x84000000 | 0xbfe61 | 0x84000000 | 0xbfe62 | 0x84000000 | 0xbfe63 | 0x84000000 | 0xbfe64 | 0x84000000 | 0xbfe65 | 0x84000000 | 0xbfe66 | 0x84000000 | 0xbfe67
1 | way 1 | set 13 | @ 0xbfc0c340 | 0x64636770 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x4 | 0x4 | 0x1 | 0x1c | 0x1d | 0x5 | 0x70736964
1 | way 1 | set 14 | @ 0xbfc0c380 | 0x79616c | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x4 | 0x4 | 0x1 | 0x20 | 0x21 | 0x6 | 0x5f676573 | 0x746f6f62
1 | way 1 | set 15 | @ 0xbfc0c3c0 | 0x646f635f | 0x65 | 0 | 0 | 0 | 0 | 0xbfc00000 | 0xbfc00000 | 0x6000 | 0x1 | 0xe | 0x1 | 0x1 | 0 | 0x5f676573 | 0x746f6f62
1 | way 1 | set 16 | @ 0xbb400 | 0x84000000 | 0xc | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 17 | @ 0xbfc0c440 | 0x70616d5f | 0x676e6970 | 0 | 0 | 0 | 0 | 0xbfc0c000 | 0xbfc0c000 | 0x3000 | 0x1 | 0xa | 0x1 | 0x1 | 0x2 | 0x5f676573 | 0x6e72656b
1 | way 1 | set 18 | @ 0x19480 | 0xaa000000 | 0xd | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 19 | @ 0xbc4c0 | 0x84000000 | 0xbfe98 | 0x84000000 | 0xbfe99 | 0x84000000 | 0xbfe9a | 0x84000000 | 0xbfe9b | 0x84000000 | 0xbfe9c | 0x84000000 | 0xbfe9d | 0x84000000 | 0xbfe9e | 0x84000000 | 0xbfe9f
1 | way 1 | set 20 | @ 0x96500 | 0x84000000 | 0xbfea0 | 0x84000000 | 0xbfea1 | 0x84000000 | 0xbfea2 | 0x84000000 | 0xbfea3 | 0x84000000 | 0xbfea4 | 0x84000000 | 0xbfea5 | 0x84000000 | 0xbfea6 | 0x84000000 | 0xbfea7
1 | way 1 | set 21 | @ 0xbc540 | 0x84000000 | 0xbfea8 | 0x84000000 | 0xbfea9 | 0x84000000 | 0xbfeaa | 0x84000000 | 0xbfeab | 0x84000000 | 0xbfeac | 0x84000000 | 0xbfead | 0x84000000 | 0xbfeae | 0x84000000 | 0xbfeaf
1 | way 1 | set 22 | @ 0x96580 | 0x84000000 | 0xbfeb0 | 0x84000000 | 0xbfeb1 | 0x84000000 | 0xbfeb2 | 0x84000000 | 0xbfeb3 | 0x84000000 | 0xbfeb4 | 0x84000000 | 0xbfeb5 | 0x84000000 | 0xbfeb6 | 0x84000000 | 0xbfeb7
1 | way 1 | set 23 | @ 0xbc5c0 | 0x84000000 | 0xbfeb8 | 0x84000000 | 0xbfeb9 | 0x84000000 | 0xbfeba | 0x84000000 | 0xbfebb | 0x84000000 | 0xbfebc | 0x84000000 | 0xbfebd | 0x84000000 | 0xbfebe | 0x84000000 | 0xbfebf
1 | way 1 | set 24 | @ 0xbfc0d600 | 0x6 | 0x10000 | 0 | 0x20000 | 0x34000 | 0 | 0x63617473 | 0x41725f6b | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 25 | @ 0xbfc0d640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x6 | 0x10000
1 | way 1 | set 26 | @ 0xbfc0d680 | 0 | 0x30000 | 0x44000 | 0 | 0x63617473 | 0x42725f6b | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 27 | @ 0xbfc0d6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x6 | 0x10000 | 0 | 0x40000
1 | way 1 | set 28 | @ 0xbc700 | 0x84000000 | 0xbfee0 | 0x84000000 | 0xbfee1 | 0x84000000 | 0xbfee2 | 0x84000000 | 0xbfee3 | 0x84000000 | 0xbfee4 | 0x84000000 | 0xbfee5 | 0x84000000 | 0xbfee6 | 0x84000000 | 0xbfee7
1 | way 1 | set 29 | @ 0xbfc0d740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x4 | 0x20 | 0 | 0x50000 | 0x64000 | 0x1
1 | way 1 | set 30 | @ 0x1a780 | 0x84000000 | 0xbfef0 | 0x84000000 | 0xbfef1 | 0x84000000 | 0xbfef2 | 0x84000000 | 0xbfef3 | 0x84000000 | 0xbfef4 | 0x84000000 | 0xbfef5 | 0x84000000 | 0xbfef6 | 0x84000000 | 0xbfef7
1 | way 1 | set 31 | @ 0x8f7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xc0000094 | 0xc0000096
1 | way 1 | set 32 | @ 0xba800 | 0x84000000 | 0xbfd00 | 0x84000000 | 0xbfd01 | 0x84000000 | 0xbfd02 | 0x84000000 | 0xbfd03 | 0x84000000 | 0xbfd04 | 0x84000000 | 0xbfd05 | 0x84000000 | 0xbfd06 | 0x84000000 | 0xbfd07
1 | way 1 | set 33 | @ 0xb8840 | 0x88000000 | 0xbc | 0x88000000 | 0xbd | 0x88000000 | 0xbe | 0x88000000 | 0xbf | 0x88000000 | 0xc0 | 0x88000000 | 0xc1 | 0x88000000 | 0xc2 | 0x88000000 | 0xc3
1 | way 1 | set 34 | @ 0xba880 | 0x84000000 | 0xbfd10 | 0x84000000 | 0xbfd11 | 0x84000000 | 0xbfd12 | 0x84000000 | 0xbfd13 | 0x84000000 | 0xbfd14 | 0x84000000 | 0xbfd15 | 0x84000000 | 0xbfd16 | 0x84000000 | 0xbfd17
1 | way 1 | set 35 | @ 0xba8c0 | 0x84000000 | 0xbfd18 | 0x84000000 | 0xbfd19 | 0x84000000 | 0xbfd1a | 0x84000000 | 0xbfd1b | 0x84000000 | 0xbfd1c | 0x84000000 | 0xbfd1d | 0x84000000 | 0xbfd1e | 0x84000000 | 0xbfd1f
1 | way 1 | set 36 | @ 0xbc900 | 0xa4400000 | 0xbff20 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 37 | @ 0xba940 | 0x84000000 | 0xbfd28 | 0x84000000 | 0xbfd29 | 0x84000000 | 0xbfd2a | 0x84000000 | 0xbfd2b | 0x84000000 | 0xbfd2c | 0x84000000 | 0xbfd2d | 0x84000000 | 0xbfd2e | 0x84000000 | 0xbfd2f
1 | way 1 | set 38 | @ 0xbd980 | 0x84000000 | 0xf30 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 39 | @ 0xba9c0 | 0x84000000 | 0xbfd38 | 0x84000000 | 0xbfd39 | 0x84000000 | 0xbfd3a | 0x84000000 | 0xbfd3b | 0x84000000 | 0xbfd3c | 0x84000000 | 0xbfd3d | 0x84000000 | 0xbfd3e | 0x84000000 | 0xbfd3f
1 | way 1 | set 40 | @ 0xbaa00 | 0x84000000 | 0xbfd40 | 0x84000000 | 0xbfd41 | 0x84000000 | 0xbfd42 | 0x84000000 | 0xbfd43 | 0x84000000 | 0xbfd44 | 0x84000000 | 0xbfd45 | 0x84000000 | 0xbfd46 | 0x84000000 | 0xbfd47
1 | way 1 | set 41 | @ 0xbaa40 | 0x84000000 | 0xbfd48 | 0x84000000 | 0xbfd49 | 0x84000000 | 0xbfd4a | 0x84000000 | 0xbfd4b | 0x84000000 | 0xbfd4c | 0x84000000 | 0xbfd4d | 0x84000000 | 0xbfd4e | 0x84000000 | 0xbfd4f
1 | way 1 | set 42 | @ 0xbfc0da80 | 0x666c65 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xf8 | 0 | 0x800000
1 | way 1 | set 43 | @ 0x18ac0 | 0x84000000 | 0xbfd58 | 0x84000000 | 0xbfd59 | 0x84000000 | 0xbfd5a | 0x84000000 | 0xbfd5b | 0x84000000 | 0xbfd5c | 0x84000000 | 0xbfd5d | 0x84000000 | 0xbfd5e | 0x84000000 | 0xbfd5f
1 | way 1 | set 44 | @ 0xbfc0db00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x1620 | 0 | 0x400000 | 0x8b000 | 0
1 | way 1 | set 45 | @ 0xbfc0cb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0x300000 | 0x8e000 | 0x12000 | 0 | 0x8 | 0 | 0x1 | 0x1f | 0x5f676573 | 0x63617473
1 | way 1 | set 46 | @ 0xbfc0db80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x2 | 0x12000 | 0xd | 0x300000 | 0x8e000 | 0 | 0x63617473 | 0x6b
1 | way 1 | set 47 | @ 0xbabc0 | 0x84000000 | 0xbfd78 | 0x84000000 | 0xbfd79 | 0x84000000 | 0xbfd7a | 0x84000000 | 0xbfd7b | 0x84000000 | 0xbfd7c | 0x84000000 | 0xbfd7d | 0x84000000 | 0xbfd7e | 0x84000000 | 0xbfd7f
1 | way 1 | set 48 | @ 0xbfc04c00 | 0x64657465 | 0x20746120 | 0x6c637963 | 0x2065 | 0x4f425b0a | 0x205d544f | 0x20554d4d | 0x69746361 | 0x69746176 | 0x63206e6f | 0x6c706d6f | 0x64657465 | 0x20746120 | 0x6c637963 | 0x2065 | 0x4f425b0a
1 | way 1 | set 49 | @ 0xbfc04c40 | 0x205d544f | 0x65686353 | 0x656c7564 | 0x69207372 | 0x6974696e | 0x73696c61 | 0x6f697461 | 0x6f63206e | 0x656c706d | 0x20646574 | 0x63207461 | 0x656c6379 | 0x20 | 0x8 | 0x8 | 0x8
1 | way 1 | set 50 | @ 0xbfc04c80 | 0x8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 51 | @ 0x6fcc0 | 0x84000000 | 0xbfd98 | 0x84000000 | 0xbfd99 | 0x84000000 | 0xbfd9a | 0x84000000 | 0xbfd9b | 0x84000000 | 0xbfd9c | 0x84000000 | 0xbfd9d | 0x84000000 | 0xbfd9e | 0x84000000 | 0xbfd9f
1 | way 1 | set 52 | @ 0xbad00 | 0x84000000 | 0xbfda0 | 0x84000000 | 0xbfda1 | 0x84000000 | 0xbfda2 | 0x84000000 | 0xbfda3 | 0x84000000 | 0xbfda4 | 0x84000000 | 0xbfda5 | 0x84000000 | 0xbfda6 | 0x84000000 | 0xbfda7
1 | way 1 | set 53 | @ 0xbad40 | 0x84000000 | 0xbfda8 | 0x84000000 | 0xbfda9 | 0x84000000 | 0xbfdaa | 0x84000000 | 0xbfdab | 0x84000000 | 0xbfdac | 0x84000000 | 0xbfdad | 0x84000000 | 0xbfdae | 0x84000000 | 0xbfdaf
1 | way 1 | set 54 | @ 0xbfc04d80 | 0x10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 55 | @ 0xbfc0ddc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x6 | 0x10000
1 | way 1 | set 56 | @ 0xbae00 | 0x84000000 | 0xbfdc0 | 0x84000000 | 0xbfdc1 | 0x84000000 | 0xbfdc2 | 0x84000000 | 0xbfdc3 | 0x84000000 | 0xbfdc4 | 0x84000000 | 0xbfdc5 | 0x84000000 | 0xbfdc6 | 0x84000000 | 0xbfdc7
1 | way 1 | set 57 | @ 0xbfc0de40 | 0 | 0x1 | 0 | 0 | 0 | 0x736e6f63 | 0x72656d75 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x1 | 0x4
1 | way 1 | set 58 | @ 0xbfc0de80 | 0xffffffff | 0x1 | 0x1 | 0 | 0 | 0 | 0x74756f72 | 0x415f7265 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x2
1 | way 1 | set 59 | @ 0xbfc0aec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xf00 | 0
1 | way 1 | set 60 | @ 0xbfc0af00 | 0xbc | 0 | 0 | 0xbfc0af10 | 0 | 0 | 0x2f | 0x1 | 0 | 0 | 0 | 0 | 0 | 0 | 0x20000 | 0x24
1 | way 1 | set 61 | @ 0xbfc04f40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x1000 | 0x2000
1 | way 1 | set 62 | @ 0xbfc04f80 | 0x3000 | 0x12000 | 0x68000 | 0x8e000 | 0xb4000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 63 | @ 0xbfc0dfc0 | 0 | 0 | 0 | 0 | 0x3 | 0xffffffff | 0 | 0x1 | 0 | 0 | 0x1 | 0x19 | 0 | 0x1 | 0x19 | 0x1
1 | way 2 | set 0 | @ 0x19000 | 0x8a000000 | 0x4 | 0x8a000000 | 0x5 | 0x8a000000 | 0x6 | 0x8a000000 | 0x7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 1 | @ 0x18040 | 0x8c000000 | 0xbfc08 | 0x8c000000 | 0xbfc09 | 0xac400000 | 0xbfc0a | 0x8c000000 | 0xbfc0b | 0xac000000 | 0xbfc0c | 0xac000000 | 0xbfc0d | 0xac000000 | 0xbfc0e | 0 | 0
1 | way 2 | set 2 | @ 0xbc080 | 0x84000000 | 0xbfe10 | 0x84000000 | 0xbfe11 | 0x84000000 | 0xbfe12 | 0x84000000 | 0xbfe13 | 0x84000000 | 0xbfe14 | 0x84000000 | 0xbfe15 | 0x84000000 | 0xbfe16 | 0x84000000 | 0xbfe17
1 | way 2 | set 3 | @ 0x930c0 | 0x8d000000 | 0xa8 | 0x8d000000 | 0xa9 | 0x8d000000 | 0xaa | 0x8d000000 | 0xab | 0x8d000000 | 0xac | 0x8d000000 | 0xad | 0x8d000000 | 0xae | 0x8d000000 | 0xaf
1 | way 2 | set 4 | @ 0xbfc0c100 | 0 | 0 | 0 | 0 | 0 | 0xbfd00000 | 0x200000 | 0x2 | 0 | 0xbfd00000 | 0x47455350 | 0x5543495f | 0 | 0 | 0 | 0
1 | way 2 | set 5 | @ 0xbc140 | 0x84000000 | 0xbfe28 | 0x84000000 | 0xbfe29 | 0x84000000 | 0xbfe2a | 0x84000000 | 0xbfe2b | 0x84000000 | 0xbfe2c | 0x84000000 | 0xbfe2d | 0x84000000 | 0xbfe2e | 0x84000000 | 0xbfe2f
1 | way 2 | set 6 | @ 0xbfc0c180 | 0x1000 | 0x2 | 0 | 0xbff10000 | 0x47455350 | 0x5954545f | 0 | 0 | 0 | 0 | 0 | 0 | 0xbff20000 | 0x1000 | 0x2 | 0
1 | way 2 | set 7 | @ 0x961c0 | 0x84000000 | 0xbfe38 | 0x84000000 | 0xbfe39 | 0x84000000 | 0xbfe3a | 0x84000000 | 0xbfe3b | 0x84000000 | 0xbfe3c | 0x84000000 | 0xbfe3d | 0x84000000 | 0xbfe3e | 0x84000000 | 0xbfe3f
1 | way 2 | set 8 | @ 0xbc200 | 0x84000000 | 0xbfe40 | 0x84000000 | 0xbfe41 | 0x84000000 | 0xbfe42 | 0x84000000 | 0xbfe43 | 0x84000000 | 0xbfe44 | 0x84000000 | 0xbfe45 | 0x84000000 | 0xbfe46 | 0x84000000 | 0xbfe47
1 | way 2 | set 9 | @ 0xbc240 | 0x84000000 | 0xbfe48 | 0x84000000 | 0xbfe49 | 0x84000000 | 0xbfe4a | 0x84000000 | 0xbfe4b | 0x84000000 | 0xbfe4c | 0x84000000 | 0xbfe4d | 0x84000000 | 0xbfe4e | 0x84000000 | 0xbfe4f
1 | way 2 | set 10 | @ 0xbc280 | 0x84000000 | 0xbfe50 | 0x84000000 | 0xbfe51 | 0x84000000 | 0xbfe52 | 0x84000000 | 0xbfe53 | 0x84000000 | 0xbfe54 | 0x84000000 | 0xbfe55 | 0x84000000 | 0xbfe56 | 0x84000000 | 0xbfe57
1 | way 2 | set 11 | @ 0xbfc0c2c0 | 0 | 0xff0000 | 0x74756f72 | 0x7265 | 0 | 0 | 0 | 0 | 0 | 0x20000000 | 0 | 0x8 | 0x9 | 0x4 | 0xf | 0xf
1 | way 2 | set 12 | @ 0xbfc0c300 | 0 | 0x6c6c6568 | 0x6f | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x5 | 0x5 | 0x1 | 0x17 | 0x18 | 0x4
1 | way 2 | set 13 | @ 0x6e340 | 0x84000000 | 0xbfe68 | 0x84000000 | 0xbfe69 | 0x84000000 | 0xbfe6a | 0x84000000 | 0xbfe6b | 0x84000000 | 0xbfe6c | 0x84000000 | 0xbfe6d | 0x84000000 | 0xbfe6e | 0x84000000 | 0xbfe6f
1 | way 2 | set 14 | @ 0xbc380 | 0x84000000 | 0xbfe70 | 0x84000000 | 0xbfe71 | 0x84000000 | 0xbfe72 | 0x84000000 | 0xbfe73 | 0x84000000 | 0xbfe74 | 0x84000000 | 0xbfe75 | 0x84000000 | 0xbfe76 | 0x84000000 | 0xbfe77
1 | way 2 | set 15 | @ 0xbc3c0 | 0x84000000 | 0xbfe78 | 0x84000000 | 0xbfe79 | 0x84000000 | 0xbfe7a | 0x84000000 | 0xbfe7b | 0x84000000 | 0xbfe7c | 0x84000000 | 0xbfe7d | 0x84000000 | 0xbfe7e | 0x84000000 | 0xbfe7f
1 | way 2 | set 16 | @ 0xbc400 | 0x84000000 | 0xbfe80 | 0x84000000 | 0xbfe81 | 0x84000000 | 0xbfe82 | 0x84000000 | 0xbfe83 | 0x84000000 | 0xbfe84 | 0x84000000 | 0xbfe85 | 0x84000000 | 0xbfe86 | 0x84000000 | 0xbfe87
1 | way 2 | set 17 | @ 0xbc440 | 0x84000000 | 0xbfe88 | 0x84000000 | 0xbfe89 | 0x84000000 | 0xbfe8a | 0x84000000 | 0xbfe8b | 0x84000000 | 0xbfe8c | 0x84000000 | 0xbfe8d | 0x84000000 | 0xbfe8e | 0x84000000 | 0xbfe8f
1 | way 2 | set 18 | @ 0xbc480 | 0x84000000 | 0xbfe90 | 0x84000000 | 0xbfe91 | 0x84000000 | 0xbfe92 | 0x84000000 | 0xbfe93 | 0x84000000 | 0xbfe94 | 0x84000000 | 0xbfe95 | 0x84000000 | 0xbfe96 | 0x84000000 | 0xbfe97
1 | way 2 | set 19 | @ 0x6e4c0 | 0x84000000 | 0xbfe98 | 0x84000000 | 0xbfe99 | 0x84000000 | 0xbfe9a | 0x84000000 | 0xbfe9b | 0x84000000 | 0xbfe9c | 0x84000000 | 0xbfe9d | 0x84000000 | 0xbfe9e | 0x84000000 | 0xbfe9f
1 | way 2 | set 20 | @ 0xbc500 | 0x84000000 | 0xbfea0 | 0x84000000 | 0xbfea1 | 0x84000000 | 0xbfea2 | 0x84000000 | 0xbfea3 | 0x84000000 | 0xbfea4 | 0x84000000 | 0xbfea5 | 0x84000000 | 0xbfea6 | 0x84000000 | 0xbfea7
1 | way 2 | set 21 | @ 0x6e540 | 0x84000000 | 0xbfea8 | 0x84000000 | 0xbfea9 | 0x84000000 | 0xbfeaa | 0x84000000 | 0xbfeab | 0x84000000 | 0xbfeac | 0x84000000 | 0xbfead | 0x84000000 | 0xbfeae | 0x84000000 | 0xbfeaf
1 | way 2 | set 22 | @ 0xbc580 | 0x84000000 | 0xbfeb0 | 0x84000000 | 0xbfeb1 | 0x84000000 | 0xbfeb2 | 0x84000000 | 0xbfeb3 | 0x84000000 | 0xbfeb4 | 0x84000000 | 0xbfeb5 | 0x84000000 | 0xbfeb6 | 0x84000000 | 0xbfeb7
1 | way 2 | set 23 | @ 0x6e5c0 | 0x84000000 | 0xbfeb8 | 0x84000000 | 0xbfeb9 | 0x84000000 | 0xbfeba | 0x84000000 | 0xbfebb | 0x84000000 | 0xbfebc | 0x84000000 | 0xbfebd | 0x84000000 | 0xbfebe | 0x84000000 | 0xbfebf
1 | way 2 | set 24 | @ 0xbc600 | 0x84000000 | 0xbfec0 | 0x84000000 | 0xbfec1 | 0x84000000 | 0xbfec2 | 0x84000000 | 0xbfec3 | 0x84000000 | 0xbfec4 | 0x84000000 | 0xbfec5 | 0x84000000 | 0xbfec6 | 0x84000000 | 0xbfec7
1 | way 2 | set 25 | @ 0xbc640 | 0x84000000 | 0xbfec8 | 0x84000000 | 0xbfec9 | 0x84000000 | 0xbfeca | 0x84000000 | 0xbfecb | 0x84000000 | 0xbfecc | 0x84000000 | 0xbfecd | 0x84000000 | 0xbfece | 0x84000000 | 0xbfecf
1 | way 2 | set 26 | @ 0xbc680 | 0x84000000 | 0xbfed0 | 0x84000000 | 0xbfed1 | 0x84000000 | 0xbfed2 | 0x84000000 | 0xbfed3 | 0x84000000 | 0xbfed4 | 0x84000000 | 0xbfed5 | 0x84000000 | 0xbfed6 | 0x84000000 | 0xbfed7
1 | way 2 | set 27 | @ 0xbc6c0 | 0x84000000 | 0xbfed8 | 0x84000000 | 0xbfed9 | 0x84000000 | 0xbfeda | 0x84000000 | 0xbfedb | 0x84000000 | 0xbfedc | 0x84000000 | 0xbfedd | 0x84000000 | 0xbfede | 0x84000000 | 0xbfedf
1 | way 2 | set 28 | @ 0x6e700 | 0x84000000 | 0xbfee0 | 0x84000000 | 0xbfee1 | 0x84000000 | 0xbfee2 | 0x84000000 | 0xbfee3 | 0x84000000 | 0xbfee4 | 0x84000000 | 0xbfee5 | 0x84000000 | 0xbfee6 | 0x84000000 | 0xbfee7
1 | way 2 | set 29 | @ 0xbc740 | 0x84000000 | 0xbfee8 | 0x84000000 | 0xbfee9 | 0x84000000 | 0xbfeea | 0x84000000 | 0xbfeeb | 0x84000000 | 0xbfeec | 0x84000000 | 0xbfeed | 0x84000000 | 0xbfeee | 0x84000000 | 0xbfeef
1 | way 2 | set 30 | @ 0x6e780 | 0x84000000 | 0xbfef0 | 0x84000000 | 0xbfef1 | 0x84000000 | 0xbfef2 | 0x84000000 | 0xbfef3 | 0x84000000 | 0xbfef4 | 0x84000000 | 0xbfef5 | 0x84000000 | 0xbfef6 | 0x84000000 | 0xbfef7
1 | way 2 | set 31 | @ 0xb57c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xc00000ba | 0xc00000bc
1 | way 2 | set 32 | @ 0xbd800 | 0x84000000 | 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 33 | @ 0x92840 | 0x88000000 | 0x96 | 0x88000000 | 0x97 | 0x88000000 | 0x98 | 0x88000000 | 0x99 | 0x88000000 | 0x9a | 0x88000000 | 0x9b | 0x88000000 | 0x9c | 0x88000000 | 0x9d
1 | way 2 | set 34 | @ 0xbc880 | 0x84000000 | 0xbff10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 35 | @ 0xbfc0d8c0 | 0 | 0 | 0 | 0 | 0 | 0x1578 | 0 | 0x400000 | 0x66000 | 0 | 0x62617470 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 36 | @ 0x96900 | 0x84000000 | 0xbff20 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 37 | @ 0xbfc04940 | 0x4e495b0a | 0x45205449 | 0x524f5252 | 0x694d205d | 0x6e697373 | 0x54502067 | 0x66204241 | 0x7620726f | 0x63617073 | 0x2065 | 0xbfc02cf0 | 0xbfc02cf0 | 0xbfc02c44 | 0xbfc02ca0 | 0xbfc02a90 | 0xbfc02b98
1 | way 2 | set 38 | @ 0x97980 | 0x84000000 | 0xf30 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 39 | @ 0xbfc0d9c0 | 0x6 | 0x10000 | 0 | 0x10000 | 0x7a000 | 0 | 0x5f63696e | 0x32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 40 | @ 0xbfc0da00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x6 | 0x4000
1 | way 2 | set 41 | @ 0x18a40 | 0x84000000 | 0xbfd48 | 0x84000000 | 0xbfd49 | 0x84000000 | 0xbfd4a | 0x84000000 | 0xbfd4b | 0x84000000 | 0xbfd4c | 0x84000000 | 0xbfd4d | 0x84000000 | 0xbfd4e | 0x84000000 | 0xbfd4f
1 | way 2 | set 42 | @ 0x71a80 | 0x84000000 | 0xf50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 43 | @ 0x6fac0 | 0x84000000 | 0xbfd58 | 0x84000000 | 0xbfd59 | 0x84000000 | 0xbfd5a | 0x84000000 | 0xbfd5b | 0x84000000 | 0xbfd5c | 0x84000000 | 0xbfd5d | 0x84000000 | 0xbfd5e | 0x84000000 | 0xbfd5f
1 | way 2 | set 44 | @ 0x94b00 | 0x84000000 | 0xbfd60 | 0x84000000 | 0xbfd61 | 0x84000000 | 0xbfd62 | 0x84000000 | 0xbfd63 | 0x84000000 | 0xbfd64 | 0x84000000 | 0xbfd65 | 0x84000000 | 0xbfd66 | 0x84000000 | 0xbfd67
1 | way 2 | set 45 | @ 0xbab40 | 0x84000000 | 0xbfd68 | 0x84000000 | 0xbfd69 | 0x84000000 | 0xbfd6a | 0x84000000 | 0xbfd6b | 0x84000000 | 0xbfd6c | 0x84000000 | 0xbfd6d | 0x84000000 | 0xbfd6e | 0x84000000 | 0xbfd6f
1 | way 2 | set 46 | @ 0xbab80 | 0x84000000 | 0xbfd70 | 0x84000000 | 0xbfd71 | 0x84000000 | 0xbfd72 | 0x84000000 | 0xbfd73 | 0x84000000 | 0xbfd74 | 0x84000000 | 0xbfd75 | 0x84000000 | 0xbfd76 | 0x84000000 | 0xbfd77
1 | way 2 | set 47 | @ 0xbfc04bc0 | 0x6d6f6320 | 0x74656c70 | 0x61206465 | 0x79632074 | 0x20656c63 | 0x203a | 0x4f425b0a | 0x205d544f | 0x69726550 | 0x72656870 | 0x20736c61 | 0x74696e69 | 0x696c6169 | 0x69746173 | 0x63206e6f | 0x6c706d6f
1 | way 2 | set 48 | @ 0xbac00 | 0x84000000 | 0xbfd80 | 0x84000000 | 0xbfd81 | 0x84000000 | 0xbfd82 | 0x84000000 | 0xbfd83 | 0x84000000 | 0xbfd84 | 0x84000000 | 0xbfd85 | 0x84000000 | 0xbfd86 | 0x84000000 | 0xbfd87
1 | way 2 | set 49 | @ 0x94c40 | 0x84000000 | 0xbfd88 | 0x84000000 | 0xbfd89 | 0x84000000 | 0xbfd8a | 0x84000000 | 0xbfd8b | 0x84000000 | 0xbfd8c | 0x84000000 | 0xbfd8d | 0x84000000 | 0xbfd8e | 0x84000000 | 0xbfd8f
1 | way 2 | set 50 | @ 0xbfc0cc80 | 0x6b | 0 | 0 | 0 | 0 | 0 | 0x10000 | 0xc6000 | 0x10000 | 0 | 0xb | 0 | 0x1 | 0x24 | 0x746f6f62 | 0x646f635f
1 | way 2 | set 51 | @ 0x94cc0 | 0x84000000 | 0xbfd98 | 0x84000000 | 0xbfd99 | 0x84000000 | 0xbfd9a | 0x84000000 | 0xbfd9b | 0x84000000 | 0xbfd9c | 0x84000000 | 0xbfd9d | 0x84000000 | 0xbfd9e | 0x84000000 | 0xbfd9f
1 | way 2 | set 52 | @ 0x94d00 | 0x84000000 | 0xbfda0 | 0x84000000 | 0xbfda1 | 0x84000000 | 0xbfda2 | 0x84000000 | 0xbfda3 | 0x84000000 | 0xbfda4 | 0x84000000 | 0xbfda5 | 0x84000000 | 0xbfda6 | 0x84000000 | 0xbfda7
1 | way 2 | set 53 | @ 0x6fd40 | 0x84000000 | 0xbfda8 | 0x84000000 | 0xbfda9 | 0x84000000 | 0xbfdaa | 0x84000000 | 0xbfdab | 0x84000000 | 0xbfdac | 0x84000000 | 0xbfdad | 0x84000000 | 0xbfdae | 0x84000000 | 0xbfdaf
1 | way 2 | set 54 | @ 0xbad80 | 0x84000000 | 0xbfdb0 | 0x84000000 | 0xbfdb1 | 0x84000000 | 0xbfdb2 | 0x84000000 | 0xbfdb3 | 0x84000000 | 0xbfdb4 | 0x84000000 | 0xbfdb5 | 0x84000000 | 0xbfdb6 | 0x84000000 | 0xbfdb7
1 | way 2 | set 55 | @ 0x6fdc0 | 0x84000000 | 0xbfdb8 | 0x84000000 | 0xbfdb9 | 0x84000000 | 0xbfdba | 0x84000000 | 0xbfdbb | 0x84000000 | 0xbfdbc | 0x84000000 | 0xbfdbd | 0x84000000 | 0xbfdbe | 0x84000000 | 0xbfdbf
1 | way 2 | set 56 | @ 0xbfc0de00 | 0 | 0x10000 | 0xc6000 | 0 | 0x646f7270 | 0x72656375 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x1 | 0x3 | 0xffffffff
1 | way 2 | set 57 | @ 0x94e40 | 0x84000000 | 0xbfdc8 | 0x84000000 | 0xbfdc9 | 0x84000000 | 0xbfdca | 0x84000000 | 0xbfdcb | 0x84000000 | 0xbfdcc | 0x84000000 | 0xbfdcd | 0x84000000 | 0xbfdce | 0x84000000 | 0xbfdcf
1 | way 2 | set 58 | @ 0xbfc04e80 | 0x300000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 59 | @ 0xbfc0dec0 | 0x5 | 0xffffffff | 0x2 | 0x1 | 0 | 0 | 0 | 0x74756f72 | 0x425f7265 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 60 | @ 0x2f00 | 0x2 | 0 | 0 | 0 | 0x101 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 61 | @ 0xbaf40 | 0x84000000 | 0xbfde8 | 0x84000000 | 0xbfde9 | 0x84000000 | 0xbfdea | 0x84000000 | 0xbfdeb | 0x84000000 | 0xbfdec | 0x84000000 | 0xbfded | 0x84000000 | 0xbfdee | 0x84000000 | 0xbfdef
1 | way 2 | set 62 | @ 0xbfc0df80 | 0 | 0 | 0x3 | 0x3 | 0xffffffff | 0 | 0x1 | 0 | 0 | 0 | 0x6e69616d | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 63 | @ 0xbafc0 | 0x84000000 | 0xbfdf8 | 0x84000000 | 0xbfdf9 | 0x84000000 | 0xbfdfa | 0x84000000 | 0xbfdfb | 0x84000000 | 0xbfdfc | 0x84000000 | 0xbfdfd | 0x84000000 | 0xbfdfe | 0x84000000 | 0xbfdff
1 | way 3 | set 0 | @ 0xb0000 | 0x400000 | 0x2a2a200a | 0x6d69202a | 0x20656761 | 0x2a206425 | 0x61202a2a | 0x61642074 | 0x3d206574 | 0x20642520 | 0xa | 0x65686365 | 0x69672063 | 0x695f7465 | 0x725f636f | 0x20646165 | 0x61206425
1 | way 3 | set 1 | @ 0x6f040 | 0x8c000000 | 0xbfc08 | 0x8c000000 | 0xbfc09 | 0xac400000 | 0xbfc0a | 0x8c000000 | 0xbfc0b | 0xac000000 | 0xbfc0c | 0xac000000 | 0xbfc0d | 0x8c000000 | 0xbfc0e | 0 | 0
1 | way 3 | set 2 | @ 0x96080 | 0x84000000 | 0xbfe10 | 0x84000000 | 0xbfe11 | 0x84000000 | 0xbfe12 | 0x84000000 | 0xbfe13 | 0x84000000 | 0xbfe14 | 0x84000000 | 0xbfe15 | 0x84000000 | 0xbfe16 | 0x84000000 | 0xbfe17
1 | way 3 | set 3 | @ 0xbc0c0 | 0x84000000 | 0xbfe18 | 0x84000000 | 0xbfe19 | 0x84000000 | 0xbfe1a | 0x84000000 | 0xbfe1b | 0x84000000 | 0xbfe1c | 0x84000000 | 0xbfe1d | 0x84000000 | 0xbfe1e | 0x84000000 | 0xbfe1f
1 | way 3 | set 4 | @ 0x6e100 | 0x84000000 | 0xbfe20 | 0x84000000 | 0xbfe21 | 0x84000000 | 0xbfe22 | 0x84000000 | 0xbfe23 | 0x84000000 | 0xbfe24 | 0x84000000 | 0xbfe25 | 0x84000000 | 0xbfe26 | 0x84000000 | 0xbfe27
1 | way 3 | set 5 | @ 0x1a140 | 0x84000000 | 0xbfe28 | 0x84000000 | 0xbfe29 | 0x84000000 | 0xbfe2a | 0x84000000 | 0xbfe2b | 0x84000000 | 0xbfe2c | 0x84000000 | 0xbfe2d | 0x84000000 | 0xbfe2e | 0x84000000 | 0xbfe2f
1 | way 3 | set 6 | @ 0x6e180 | 0x84000000 | 0xbfe30 | 0x84000000 | 0xbfe31 | 0x84000000 | 0xbfe32 | 0x84000000 | 0xbfe33 | 0x84000000 | 0xbfe34 | 0x84000000 | 0xbfe35 | 0x84000000 | 0xbfe36 | 0x84000000 | 0xbfe37
1 | way 3 | set 7 | @ 0xbfc0c1c0 | 0xbff20000 | 0x47455350 | 0x414d445f | 0 | 0 | 0 | 0 | 0 | 0 | 0xf30000 | 0x1000 | 0x2 | 0 | 0xf30000 | 0x47455350 | 0x43494e5f
1 | way 3 | set 8 | @ 0x1a200 | 0x84000000 | 0xbfe40 | 0x84000000 | 0xbfe41 | 0x84000000 | 0xbfe42 | 0x84000000 | 0xbfe43 | 0x84000000 | 0xbfe44 | 0x84000000 | 0xbfe45 | 0x84000000 | 0xbfe46 | 0x84000000 | 0xbfe47
1 | way 3 | set 9 | @ 0x1a240 | 0x84000000 | 0xbfe48 | 0x84000000 | 0xbfe49 | 0x84000000 | 0xbfe4a | 0x84000000 | 0xbfe4b | 0x84000000 | 0xbfe4c | 0x84000000 | 0xbfe4d | 0x84000000 | 0xbfe4e | 0x84000000 | 0xbfe4f
1 | way 3 | set 10 | @ 0x1a280 | 0x84000000 | 0xbfe50 | 0x84000000 | 0xbfe51 | 0x84000000 | 0xbfe52 | 0x84000000 | 0xbfe53 | 0x84000000 | 0xbfe54 | 0x84000000 | 0xbfe55 | 0x84000000 | 0xbfe56 | 0x84000000 | 0xbfe57
1 | way 3 | set 11 | @ 0x6e2c0 | 0x84000000 | 0xbfe58 | 0x84000000 | 0xbfe59 | 0x84000000 | 0xbfe5a | 0x84000000 | 0xbfe5b | 0x84000000 | 0xbfe5c | 0x84000000 | 0xbfe5d | 0x84000000 | 0xbfe5e | 0x84000000 | 0xbfe5f
1 | way 3 | set 12 | @ 0x6e300 | 0x84000000 | 0xbfe60 | 0x84000000 | 0xbfe61 | 0x84000000 | 0xbfe62 | 0x84000000 | 0xbfe63 | 0x84000000 | 0xbfe64 | 0x84000000 | 0xbfe65 | 0x84000000 | 0xbfe66 | 0x84000000 | 0xbfe67
1 | way 3 | set 13 | @ 0x96340 | 0x84000000 | 0xbfe68 | 0x84000000 | 0xbfe69 | 0x84000000 | 0xbfe6a | 0x84000000 | 0xbfe6b | 0x84000000 | 0xbfe6c | 0x84000000 | 0xbfe6d | 0x84000000 | 0xbfe6e | 0x84000000 | 0xbfe6f
1 | way 3 | set 14 | @ 0x6e380 | 0x84000000 | 0xbfe70 | 0x84000000 | 0xbfe71 | 0x84000000 | 0xbfe72 | 0x84000000 | 0xbfe73 | 0x84000000 | 0xbfe74 | 0x84000000 | 0xbfe75 | 0x84000000 | 0xbfe76 | 0x84000000 | 0xbfe77
1 | way 3 | set 15 | @ 0x6e3c0 | 0x84000000 | 0xbfe78 | 0x84000000 | 0xbfe79 | 0x84000000 | 0xbfe7a | 0x84000000 | 0xbfe7b | 0x84000000 | 0xbfe7c | 0x84000000 | 0xbfe7d | 0x84000000 | 0xbfe7e | 0x84000000 | 0xbfe7f
1 | way 3 | set 16 | @ 0x96400 | 0x84000000 | 0xbfe80 | 0x84000000 | 0xbfe81 | 0x84000000 | 0xbfe82 | 0x84000000 | 0xbfe83 | 0x84000000 | 0xbfe84 | 0x84000000 | 0xbfe85 | 0x84000000 | 0xbfe86 | 0x84000000 | 0xbfe87
1 | way 3 | set 17 | @ 0x6e440 | 0x84000000 | 0xbfe88 | 0x84000000 | 0xbfe89 | 0x84000000 | 0xbfe8a | 0x84000000 | 0xbfe8b | 0x84000000 | 0xbfe8c | 0x84000000 | 0xbfe8d | 0x84000000 | 0xbfe8e | 0x84000000 | 0xbfe8f
1 | way 3 | set 18 | @ 0x96480 | 0x84000000 | 0xbfe90 | 0x84000000 | 0xbfe91 | 0x84000000 | 0xbfe92 | 0x84000000 | 0xbfe93 | 0x84000000 | 0xbfe94 | 0x84000000 | 0xbfe95 | 0x84000000 | 0xbfe96 | 0x84000000 | 0xbfe97
1 | way 3 | set 19 | @ 0x964c0 | 0x84000000 | 0xbfe98 | 0x84000000 | 0xbfe99 | 0x84000000 | 0xbfe9a | 0x84000000 | 0xbfe9b | 0x84000000 | 0xbfe9c | 0x84000000 | 0xbfe9d | 0x84000000 | 0xbfe9e | 0x84000000 | 0xbfe9f
1 | way 3 | set 20 | @ 0x6e500 | 0x84000000 | 0xbfea0 | 0x84000000 | 0xbfea1 | 0x84000000 | 0xbfea2 | 0x84000000 | 0xbfea3 | 0x84000000 | 0xbfea4 | 0x84000000 | 0xbfea5 | 0x84000000 | 0xbfea6 | 0x84000000 | 0xbfea7
1 | way 3 | set 21 | @ 0x96540 | 0x84000000 | 0xbfea8 | 0x84000000 | 0xbfea9 | 0x84000000 | 0xbfeaa | 0x84000000 | 0xbfeab | 0x84000000 | 0xbfeac | 0x84000000 | 0xbfead | 0x84000000 | 0xbfeae | 0x84000000 | 0xbfeaf
1 | way 3 | set 22 | @ 0x6e580 | 0x84000000 | 0xbfeb0 | 0x84000000 | 0xbfeb1 | 0x84000000 | 0xbfeb2 | 0x84000000 | 0xbfeb3 | 0x84000000 | 0xbfeb4 | 0x84000000 | 0xbfeb5 | 0x84000000 | 0xbfeb6 | 0x84000000 | 0xbfeb7
1 | way 3 | set 23 | @ 0x965c0 | 0x84000000 | 0xbfeb8 | 0x84000000 | 0xbfeb9 | 0x84000000 | 0xbfeba | 0x84000000 | 0xbfebb | 0x84000000 | 0xbfebc | 0x84000000 | 0xbfebd | 0x84000000 | 0xbfebe | 0x84000000 | 0xbfebf
1 | way 3 | set 24 | @ 0x6e600 | 0x84000000 | 0xbfec0 | 0x84000000 | 0xbfec1 | 0x84000000 | 0xbfec2 | 0x84000000 | 0xbfec3 | 0x84000000 | 0xbfec4 | 0x84000000 | 0xbfec5 | 0x84000000 | 0xbfec6 | 0x84000000 | 0xbfec7
1 | way 3 | set 25 | @ 0x6e640 | 0x84000000 | 0xbfec8 | 0x84000000 | 0xbfec9 | 0x84000000 | 0xbfeca | 0x84000000 | 0xbfecb | 0x84000000 | 0xbfecc | 0x84000000 | 0xbfecd | 0x84000000 | 0xbfece | 0x84000000 | 0xbfecf
1 | way 3 | set 26 | @ 0x6e680 | 0x84000000 | 0xbfed0 | 0x84000000 | 0xbfed1 | 0x84000000 | 0xbfed2 | 0x84000000 | 0xbfed3 | 0x84000000 | 0xbfed4 | 0x84000000 | 0xbfed5 | 0x84000000 | 0xbfed6 | 0x84000000 | 0xbfed7
1 | way 3 | set 27 | @ 0x6e6c0 | 0x84000000 | 0xbfed8 | 0x84000000 | 0xbfed9 | 0x84000000 | 0xbfeda | 0x84000000 | 0xbfedb | 0x84000000 | 0xbfedc | 0x84000000 | 0xbfedd | 0x84000000 | 0xbfede | 0x84000000 | 0xbfedf
1 | way 3 | set 28 | @ 0x96700 | 0x84000000 | 0xbfee0 | 0x84000000 | 0xbfee1 | 0x84000000 | 0xbfee2 | 0x84000000 | 0xbfee3 | 0x84000000 | 0xbfee4 | 0x84000000 | 0xbfee5 | 0x84000000 | 0xbfee6 | 0x84000000 | 0xbfee7
1 | way 3 | set 29 | @ 0x6e740 | 0x84000000 | 0xbfee8 | 0x84000000 | 0xbfee9 | 0x84000000 | 0xbfeea | 0x84000000 | 0xbfeeb | 0x84000000 | 0xbfeec | 0x84000000 | 0xbfeed | 0x84000000 | 0xbfeee | 0x84000000 | 0xbfeef
1 | way 3 | set 30 | @ 0x96780 | 0x84000000 | 0xbfef0 | 0x84000000 | 0xbfef1 | 0x84000000 | 0xbfef2 | 0x84000000 | 0xbfef3 | 0x84000000 | 0xbfef4 | 0x84000000 | 0xbfef5 | 0x84000000 | 0xbfef6 | 0x84000000 | 0xbfef7
1 | way 3 | set 31 | @ 0x137c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xc0000018 | 0xc000001a
1 | way 3 | set 32 | @ 0x97800 | 0x84000000 | 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 3 | set 33 | @ 0xba840 | 0x84000000 | 0xbfd08 | 0x84000000 | 0xbfd09 | 0x84000000 | 0xbfd0a | 0x84000000 | 0xbfd0b | 0x84000000 | 0xbfd0c | 0x84000000 | 0xbfd0d | 0x84000000 | 0xbfd0e | 0x84000000 | 0xbfd0f
1 | way 3 | set 34 | @ 0x96880 | 0x84000000 | 0xbff10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 3 | set 35 | @ 0x6f8c0 | 0x84000000 | 0xbfd18 | 0x84000000 | 0xbfd19 | 0x84000000 | 0xbfd1a | 0x84000000 | 0xbfd1b | 0x84000000 | 0xbfd1c | 0x84000000 | 0xbfd1d | 0x84000000 | 0xbfd1e | 0x84000000 | 0xbfd1f
1 | way 3 | set 36 | @ 0x1a900 | 0xa4400000 | 0xbff20 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 3 | set 37 | @ 0x6f940 | 0x84000000 | 0xbfd28 | 0x84000000 | 0xbfd29 | 0x84000000 | 0xbfd2a | 0x84000000 | 0xbfd2b | 0x84000000 | 0xbfd2c | 0x84000000 | 0xbfd2d | 0x84000000 | 0xbfd2e | 0x84000000 | 0xbfd2f
1 | way 3 | set 38 | @ 0xbfc04980 | 0xbfc02cf0 | 0xbfc02b28 | 0xbfc02c54 | 0xbfc02bc8 | 0x4f425b0a | 0x4520544f | 0x524f5252 | 0x694d205d | 0x6e697373 | 0x41522067 | 0x7370204d | 0x69206765 | 0x6c63206e | 0x65747375 | 0x2072 | 0x4f425b0a
1 | way 3 | set 39 | @ 0x6f9c0 | 0x84000000 | 0xbfd38 | 0x84000000 | 0xbfd39 | 0x84000000 | 0xbfd3a | 0x84000000 | 0xbfd3b | 0x84000000 | 0xbfd3c | 0x84000000 | 0xbfd3d | 0x84000000 | 0xbfd3e | 0x84000000 | 0xbfd3f
1 | way 3 | set 40 | @ 0x6fa00 | 0x84000000 | 0xbfd40 | 0x84000000 | 0xbfd41 | 0x84000000 | 0xbfd42 | 0x84000000 | 0xbfd43 | 0x84000000 | 0xbfd44 | 0x84000000 | 0xbfd45 | 0x84000000 | 0xbfd46 | 0x84000000 | 0xbfd47
1 | way 3 | set 41 | @ 0x6fa40 | 0x84000000 | 0xbfd48 | 0x84000000 | 0xbfd49 | 0x84000000 | 0xbfd4a | 0x84000000 | 0xbfd4b | 0x84000000 | 0xbfd4c | 0x84000000 | 0xbfd4d | 0x84000000 | 0xbfd4e | 0x84000000 | 0xbfd4f
1 | way 3 | set 42 | @ 0xbaa80 | 0x84000000 | 0xbfd50 | 0x84000000 | 0xbfd51 | 0x84000000 | 0xbfd52 | 0x84000000 | 0xbfd53 | 0x84000000 | 0xbfd54 | 0x84000000 | 0xbfd55 | 0x84000000 | 0xbfd56 | 0x84000000 | 0xbfd57
1 | way 3 | set 43 | @ 0x94ac0 | 0x84000000 | 0xbfd58 | 0x84000000 | 0xbfd59 | 0x84000000 | 0xbfd5a | 0x84000000 | 0xbfd5b | 0x84000000 | 0xbfd5c | 0x84000000 | 0xbfd5d | 0x84000000 | 0xbfd5e | 0x84000000 | 0xbfd5f
1 | way 3 | set 44 | @ 0x18b00 | 0x84000000 | 0xbfd60 | 0x84000000 | 0xbfd61 | 0x84000000 | 0xbfd62 | 0x84000000 | 0xbfd63 | 0x84000000 | 0xbfd64 | 0x84000000 | 0xbfd65 | 0x84000000 | 0xbfd66 | 0x84000000 | 0xbfd67
1 | way 3 | set 45 | @ 0x6fb40 | 0x84000000 | 0xbfd68 | 0x84000000 | 0xbfd69 | 0x84000000 | 0xbfd6a | 0x84000000 | 0xbfd6b | 0x84000000 | 0xbfd6c | 0x84000000 | 0xbfd6d | 0x84000000 | 0xbfd6e | 0x84000000 | 0xbfd6f
1 | way 3 | set 46 | @ 0x6fb80 | 0x84000000 | 0xbfd70 | 0x84000000 | 0xbfd71 | 0x84000000 | 0xbfd72 | 0x84000000 | 0xbfd73 | 0x84000000 | 0xbfd74 | 0x84000000 | 0xbfd75 | 0x84000000 | 0xbfd76 | 0x84000000 | 0xbfd77
1 | way 3 | set 47 | @ 0x94bc0 | 0x84000000 | 0xbfd78 | 0x84000000 | 0xbfd79 | 0x84000000 | 0xbfd7a | 0x84000000 | 0xbfd7b | 0x84000000 | 0xbfd7c | 0x84000000 | 0xbfd7d | 0x84000000 | 0xbfd7e | 0x84000000 | 0xbfd7f
1 | way 3 | set 48 | @ 0x6fc00 | 0x84000000 | 0xbfd80 | 0x84000000 | 0xbfd81 | 0x84000000 | 0xbfd82 | 0x84000000 | 0xbfd83 | 0x84000000 | 0xbfd84 | 0x84000000 | 0xbfd85 | 0x84000000 | 0xbfd86 | 0x84000000 | 0xbfd87
1 | way 3 | set 49 | @ 0xbac40 | 0x84000000 | 0xbfd88 | 0x84000000 | 0xbfd89 | 0x84000000 | 0xbfd8a | 0x84000000 | 0xbfd8b | 0x84000000 | 0xbfd8c | 0x84000000 | 0xbfd8d | 0x84000000 | 0xbfd8e | 0x84000000 | 0xbfd8f
1 | way 3 | set 50 | @ 0xbfc0dc80 | 0 | 0 | 0 | 0 | 0 | 0x1a8 | 0 | 0x800000 | 0xb0000 | 0 | 0x65646f63 | 0 | 0 | 0 | 0 | 0
1 | way 3 | set 51 | @ 0xbacc0 | 0x84000000 | 0xbfd98 | 0x84000000 | 0xbfd99 | 0x84000000 | 0xbfd9a | 0x84000000 | 0xbfd9b | 0x84000000 | 0xbfd9c | 0x84000000 | 0xbfd9d | 0x84000000 | 0xbfd9e | 0x84000000 | 0xbfd9f
1 | way 3 | set 52 | @ 0xbcd00 | 0x84000000 | 0xbffa0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 3 | set 53 | @ 0x94d40 | 0x84000000 | 0xbfda8 | 0x84000000 | 0xbfda9 | 0x84000000 | 0xbfdaa | 0x84000000 | 0xbfdab | 0x84000000 | 0xbfdac | 0x84000000 | 0xbfdad | 0x84000000 | 0xbfdae | 0x84000000 | 0xbfdaf
1 | way 3 | set 54 | @ 0x6fd80 | 0x84000000 | 0xbfdb0 | 0x84000000 | 0xbfdb1 | 0x84000000 | 0xbfdb2 | 0x84000000 | 0xbfdb3 | 0x84000000 | 0xbfdb4 | 0x84000000 | 0xbfdb5 | 0x84000000 | 0xbfdb6 | 0x84000000 | 0xbfdb7
1 | way 3 | set 55 | @ 0x94dc0 | 0x84000000 | 0xbfdb8 | 0x84000000 | 0xbfdb9 | 0x84000000 | 0xbfdba | 0x84000000 | 0xbfdbb | 0x84000000 | 0xbfdbc | 0x84000000 | 0xbfdbd | 0x84000000 | 0xbfdbe | 0x84000000 | 0xbfdbf
1 | way 3 | set 56 | @ 0x6fe00 | 0x84000000 | 0xbfdc0 | 0x84000000 | 0xbfdc1 | 0x84000000 | 0xbfdc2 | 0x84000000 | 0xbfdc3 | 0x84000000 | 0xbfdc4 | 0x84000000 | 0xbfdc5 | 0x84000000 | 0xbfdc6 | 0x84000000 | 0xbfdc7
1 | way 3 | set 57 | @ 0xbae40 | 0x84000000 | 0xbfdc8 | 0x84000000 | 0xbfdc9 | 0x84000000 | 0xbfdca | 0x84000000 | 0xbfdcb | 0x84000000 | 0xbfdcc | 0x84000000 | 0xbfdcd | 0x84000000 | 0xbfdce | 0x84000000 | 0xbfdcf
1 | way 3 | set 58 | @ 0x94e80 | 0x84000000 | 0xbfdd0 | 0x84000000 | 0xbfdd1 | 0x84000000 | 0xbfdd2 | 0x84000000 | 0xbfdd3 | 0x84000000 | 0xbfdd4 | 0x84000000 | 0xbfdd5 | 0x84000000 | 0xbfdd6 | 0x84000000 | 0xbfdd7
1 | way 3 | set 59 | @ 0x94ec0 | 0x84000000 | 0xbfdd8 | 0x84000000 | 0xbfdd9 | 0x84000000 | 0xbfdda | 0x84000000 | 0xbfddb | 0x84000000 | 0xbfddc | 0x84000000 | 0xbfddd | 0x84000000 | 0xbfdde | 0x84000000 | 0xbfddf
1 | way 3 | set 60 | @ 0xf00 | 0x1 | 0 | 0x101 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x3 | 0x10003 | 0x20003 | 0x30003 | 0x40003 | 0x50003
1 | way 3 | set 61 | @ 0xbfc0df40 | 0 | 0x2 | 0x3 | 0xffffffff | 0 | 0x1 | 0 | 0 | 0 | 0x6e69616d | 0 | 0 | 0 | 0 | 0 | 0
1 | way 3 | set 62 | @ 0xbdf80 | 0x84000000 | 0xff0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 3 | set 63 | @ 0x6ffc0 | 0x84000000 | 0xbfdf8 | 0x84000000 | 0xbfdf9 | 0x84000000 | 0xbfdfa | 0x84000000 | 0xbfdfb | 0x84000000 | 0xbfdfc | 0x84000000 | 0xbfdfd | 0x84000000 | 0xbfdfe | 0x84000000 | 0xbfdff
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_IDLE> Read request: srcid = 1 / address = 0x18040 / pktid = 0x1 / nwords = 16
****************** cycle 1701398 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x4
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
****************** cycle 1701399 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 2 / set = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_LOCK> Accessing directory:  address = 0x18040 / hit = 1 / count = 2 / is_cnt = 0
****************** cycle 1701400 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_REQ> Requesting HEAP lock 
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0x8c000000 / cpt = 0
****************** cycle 1701401 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_LOCK> Update directory: tag = 0x6 set = 1 way = 0 count = 3 is_cnt = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc08 / cpt = 1
****************** cycle 1701402 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_WRITE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x8c000000 / WAY = 0 / SET = 1 / WORD = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_WRITE> Add an entry in the heap: owner_id = 1 owner_ins = 0
****************** cycle 1701403 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc08 / WAY = 0 / SET = 1 / WORD = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0x8c000000 / cpt = 2
****************** cycle 1701404 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x8c000000 / WAY = 0 / SET = 1 / WORD = 2
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d0 / for address 0x000019000
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc09 / cpt = 3
****************** cycle 1701405 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc09 / WAY = 0 / SET = 1 / WORD = 3
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019000 srcid = 0d0 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0xac400000 / cpt = 4
****************** cycle 1701406 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xac400000 / WAY = 0 / SET = 1 / WORD = 4
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019000 srcid = 0d0 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 0 addr = 0x19000 wdata = 0x8a000000 eop = 0 cpt  = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc0a / cpt = 5
****************** cycle 1701407 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc0a / WAY = 0 / SET = 1 / WORD = 5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 0 addr = 0x19000 wdata = 0xaa000000 eop = 1 cpt  = 1
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0x8c000000 / cpt = 6
****************** cycle 1701408 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x8c000000 / WAY = 0 / SET = 1 / WORD = 6
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc0b / cpt = 7
****************** cycle 1701409 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc0b / WAY = 0 / SET = 1 / WORD = 7
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0xac000000 / cpt = 8
****************** cycle 1701410 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xac000000 / WAY = 0 / SET = 1 / WORD = 8
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19000 / hit = 1 / count = 1 / is_cnt = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc0c / cpt = 9
****************** cycle 1701411 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc0c / WAY = 0 / SET = 1 / WORD = 9
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0xac000000 / cpt = 10
****************** cycle 1701412 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xac000000 / WAY = 0 / SET = 1 / WORD = 10
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 2315255808 / actual value = 2315255808 / forced_fail = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc0d / cpt = 11
****************** cycle 1701413 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_DIR_HIT_WRITE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc0d / WAY = 0 / SET = 1 / WORD = 11
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0xac000000 / cpt = 12
****************** cycle 1701414 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_UPT_LOCK | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xac000000 / WAY = 0 / SET = 1 / WORD = 12
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc0e / cpt = 13
****************** cycle 1701415 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_UPT_LOCK | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc0e / WAY = 0 / SET = 1 / WORD = 13
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_UPT_LOCK> Register multi-update transaction in UPT / wok = 1 / nline  = 0x00000000640 / count = 0x1
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 14
****************** cycle 1701416 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_UPT_HEAP_LOCK | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 1 / WORD = 14
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 15
****************** cycle 1701417 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_RSP | WRITE_IDLE | CAS_UPT_HEAP_LOCK | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 1 / WORD = 15
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_RSP> Request the TGT_RSP FSM to return data: rsrcid = 1 / address = 0x18040 / nwords = 16
  <MEMC memc_0_0.CAS_UPT_HEAP_LOCK> Get access to the heap
****************** cycle 1701418 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_UPT_REQ | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DIR_UPDT> Switch slot to VALID state PADDR = 0x000018058 / WAY = 0 / SET = 1
1 | way 0 | set 0 | @ 0xbfc0c000 | 0xbabef00d | 0x1 | 0x1 | 0x1 | 0xf | 0x4 | 0 | 0 | 0 | 0 | 0xb | 0x24 | 0x25 | 0x7 | 0x4 | 0x1c
1 | way 0 | set 1 | @ 0x18040 | 0x8c000000 | 0xbfc08 | 0x8c000000 | 0xbfc09 | 0xac400000 | 0xbfc0a | 0x8c000000 | 0xbfc0b | 0xac000000 | 0xbfc0c | 0xac000000 | 0xbfc0d | 0xac000000 | 0xbfc0e | 0 | 0
0 | way 0 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 18 | @ 0x19480 | 0xaa000000 | 0xd | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 31 | @ 0x137c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xc0000018 | 0xc000001a
0 | way 0 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 62 | @ 0xbfc04f80 | 0x3000 | 0x12000 | 0x68000 | 0x8e000 | 0xb4000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 0 | @ 0x18000 | 0xae000000 | 0xbfc00 | 0x8e000000 | 0xbfc01 | 0x8e000000 | 0xbfc02 | 0xae000000 | 0xbfc03 | 0xae400000 | 0xbfc04 | 0x8e000000 | 0xbfc05 | 0 | 0 | 0 | 0
0 | way 1 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 0 | @ 0x13000 | 0xc0000019 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 0 | @ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_IDLE> Read request: srcid = 2 / address = 0x18040 / pktid = 0x1 / nwords = 16
  <MEMC memc_0_0.CAS_UPT_REQ> Send the first update request to CC_SEND FSM  / address = 0x19000 / wdata = 0xaa000000 / srcid = 0 / inst = 0
****************** cycle 1701419 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8c000000 PTE_PPN = 0xbfc0b
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
****************** cycle 1701420 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_HEADER | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB: way = 0 / set = 3
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
****************** cycle 1701421 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_LOCK> Accessing directory:  address = 0x18040 / hit = 1 / count = 3 / is_cnt = 0
  <MEMC memc_0_0.CC_SEND_CAS_UPDT_NLINE> Multicast-Update for line 0d1600
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0x8c000000 / cpt = 0
****************** cycle 1701422 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_DATA | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_REQ> Requesting HEAP lock 
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc08 / cpt = 1
****************** cycle 1701423 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_HEADER | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x8c000000 / WAY = 0 / SET = 1 / WORD = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_REQ> Requesting HEAP lock 
****************** cycle 1701424 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc08 / WAY = 0 / SET = 1 / WORD = 1
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_LOCK> Update directory: tag = 0x6 set = 1 way = 0 count = 4 is_cnt = 1
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0x8c000000 / cpt = 2
****************** cycle 1701425 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_ERASE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x8c000000 / WAY = 0 / SET = 1 / WORD = 2
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000018058
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc09 / cpt = 3
****************** cycle 1701426 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_READ | READ_HEAP_LAST | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc09 / WAY = 0 / SET = 1 / WORD = 3
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000018058 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08c000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0xac400000 / cpt = 4
****************** cycle 1701427 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_CC_CHECK> paddr = 0x000019000 r_dcache_vci_paddr = 0x000019000 mask = 0x0ffffffc0 (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) = 0 (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT) = 0 ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) = 0x1
  <PROC proc_0_0_0 DCACHE_CC_CHECK> Coherence request received: PADDR = 0x000019000 / TYPE = 3 / HIT = 1
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 2889875456 / WAY = 0 / SET = 1 / WORD = 4
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000018058 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0ac000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x18058 wdata = 0x8c000000 eop = 0 cpt  = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc0a / cpt = 5
****************** cycle 1701428 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc0a / WAY = 0 / SET = 1 / WORD = 5
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x18058 wdata = 0xac000000 eop = 1 cpt  = 1
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0x8c000000 / cpt = 6
****************** cycle 1701429 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x8c000000 / WAY = 0 / SET = 1 / WORD = 6
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc0b / cpt = 7
****************** cycle 1701430 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc0b / WAY = 0 / SET = 1 / WORD = 7
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0xac000000 / cpt = 8
****************** cycle 1701431 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xac000000 / WAY = 0 / SET = 1 / WORD = 8
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x18058 / hit = 1 / count = 4 / is_cnt = 1
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc0c / cpt = 9
****************** cycle 1701432 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc0c / WAY = 0 / SET = 1 / WORD = 9
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0xac000000 / cpt = 10
****************** cycle 1701433 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xac000000 / WAY = 0 / SET = 1 / WORD = 10
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 2348810240 / actual value = 2348810240 / forced_fail = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc0d / cpt = 11
****************** cycle 1701434 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_DIR_HIT_WRITE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc0d / WAY = 0 / SET = 1 / WORD = 11
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0xac000000 / cpt = 12
****************** cycle 1701435 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_BC_TRT_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xac000000 / WAY = 0 / SET = 1 / WORD = 12
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc0e / cpt = 13
****************** cycle 1701436 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_BC_TRT_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc0e / WAY = 0 / SET = 1 / WORD = 13
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 14
****************** cycle 1701437 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_BC_UPT_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_CC_UPDT> Write one word / WAY = 2 / SET = 0 / WORD = 0 / VALUE = 0xaa000000
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 1 / WORD = 14
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_BC_UPT_LOCK> Register a broadcast inval transaction in UPT / nline = 0d1537 / count = 4 / upt_index = 1
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 15
****************** cycle 1701438 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_RSP | WRITE_IDLE | CAS_BC_DIR_INVAL | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 1 / WORD = 15
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_RSP> Request the TGT_RSP FSM to return data: rsrcid = 2 / address = 0x18040 / nwords = 16
  <MEMC memc_0_0.CAS_BC_DIR_INVAL> Register the PUT in TRT and invalidate DIR entry / nline = 0x601 / set = 1 / way = 0
****************** cycle 1701439 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_BC_CC_SEND | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DIR_UPDT> Switch slot to VALID state PADDR = 0x000018058 / WAY = 0 / SET = 1
1 | way 0 | set 0 | @ 0xbfc0c000 | 0xbabef00d | 0x1 | 0x1 | 0x1 | 0xf | 0x4 | 0 | 0 | 0 | 0 | 0xb | 0x24 | 0x25 | 0x7 | 0x4 | 0x1c
1 | way 0 | set 1 | @ 0x18040 | 0x8c000000 | 0xbfc08 | 0x8c000000 | 0xbfc09 | 0xac400000 | 0xbfc0a | 0x8c000000 | 0xbfc0b | 0xac000000 | 0xbfc0c | 0xac000000 | 0xbfc0d | 0xac000000 | 0xbfc0e | 0 | 0
0 | way 0 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 18 | @ 0x19480 | 0xaa000000 | 0xd | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 31 | @ 0x137c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xc0000018 | 0xc000001a
0 | way 0 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 61 | @ 0xbfc04f40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x1000 | 0x2000
1 | way 0 | set 62 | @ 0xbfc04f80 | 0x3000 | 0x12000 | 0x68000 | 0x8e000 | 0xb4000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 0 | @ 0x18000 | 0xae000000 | 0xbfc00 | 0x8e000000 | 0xbfc01 | 0x8e000000 | 0xbfc02 | 0xae000000 | 0xbfc03 | 0xae400000 | 0xbfc04 | 0x8e000000 | 0xbfc05 | 0 | 0 | 0 | 0
0 | way 1 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 0 | @ 0x13000 | 0xc0000019 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 0 | @ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701440 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_BC_XRAM_REQ | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8c000000 PTE_PPN = 0xbfc0b
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_BC_XRAM_REQ> Request a PUT transaction to IXR_CMD FSM / nline = 0x601 / trt_index = 0
****************** cycle 1701441 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_BRDCAST_HEADER | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB: way = 0 / set = 3
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701442 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_BRDCAST_NLINE | CC_RECEIVE_MULTI_ACK | MULTI_ACK_IDLE | IXR_CMD_CAS_NLINE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_CMD_CAS_NLINE> Send a put request to xram
  <MEMC memc_0_0.CC_SEND_CAS_BRDCAST_NLINE> Broadcast-Inval for line 0x00000000601
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0x8c000000 / cpt = 0
****************** cycle 1701443 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_CAS_NLINE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.MULTI_ACK_IDLE> Response for UPT entry 
  <MEMC memc_0_0.IXR_CMD_CAS_NLINE> Send a put request to xram
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc08 / cpt = 1
****************** cycle 1701444 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_UPT_LOCK | IXR_CMD_CAS_NLINE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x8c000000 / WAY = 0 / SET = 1 / WORD = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_CMD_CAS_NLINE> Send a put request to xram
****************** cycle 1701445 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_UPT_LOCK | IXR_CMD_CAS_NLINE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc08 / WAY = 0 / SET = 1 / WORD = 1
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.MULTI_ACK_UPT_LOCK> Decrement the responses counter for UPT: entry = 0 / rsp_count = 0
  <MEMC memc_0_0.IXR_CMD_CAS_NLINE> Send a put request to xram
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0x8c000000 / cpt = 2
****************** cycle 1701446 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_UPT_CLEAR | IXR_CMD_CAS_NLINE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x8c000000 / WAY = 0 / SET = 1 / WORD = 2
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d1 / for address 0x000018058
  <MEMC memc_0_0.MULTI_ACK_UPT_CLEAR> Clear UPT entry 0
  <MEMC memc_0_0.IXR_CMD_CAS_NLINE> Send a put request to xram
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc09 / cpt = 3
****************** cycle 1701447 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_WRITE_RSP | IXR_CMD_CAS_NLINE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc09 / WAY = 0 / SET = 1 / WORD = 3
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000018058 srcid = 0d1 trdid = 0d0 pktid = 0d5 wdata = 0x08c000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.MULTI_ACK_WRITE_RSP> Request TGT_RSP FSM to send a response to srcid 0
  <MEMC memc_0_0.IXR_CMD_CAS_NLINE> Send a put request to xram
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0xac400000 / cpt = 4
****************** cycle 1701448 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_CAS_NLINE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xac400000 / WAY = 0 / SET = 1 / WORD = 4
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000018058 srcid = 0d1 trdid = 0d0 pktid = 0d5 wdata = 0x0ac000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.IXR_CMD_CAS_NLINE> Send a put request to xram
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 1 addr = 0x18058 wdata = 0x8c000000 eop = 0 cpt  = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc0a / cpt = 5
****************** cycle 1701449 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_BRDCAST_HEADER | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_CAS_NLINE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc0a / WAY = 0 / SET = 1 / WORD = 5
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_CMD_CAS_NLINE> Send a put request to xram
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 1 addr = 0x18058 wdata = 0xac000000 eop = 1 cpt  = 1
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0x8c000000 / cpt = 6
****************** cycle 1701450 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_BRDCAST_NLINE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_CAS_NLINE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x8c000000 / WAY = 0 / SET = 1 / WORD = 6
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_CC_CHECK> paddr = 0d98368 r_dcache_vci_paddr = 0d98392 mask = 0d4294967232 (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) = 0 (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT) = 0 ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) = 1
  <PROC proc_0_0_3 DCACHE_CC_CHECK> Coherence request received: PADDR = 0x000018040 / TYPE = 1 / HIT = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_CMD_CAS_NLINE> Send a put request to xram
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc0b / cpt = 7
****************** cycle 1701451 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_CAS_NLINE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc0b / WAY = 0 / SET = 1 / WORD = 7
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_CMD_CAS_NLINE> Send a put request to xram
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x18058 / hit = 0 / count = 0 / is_cnt = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0xac000000 / cpt = 8
****************** cycle 1701452 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp  invalid no error ins 0>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_CC_CHECK | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_MISS_TRT_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_CAS_NLINE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xac000000 / WAY = 0 / SET = 1 / WORD = 8
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_CMD_CAS_NLINE> Send a put request to xram
  <MEMC memc_0_0.CAS_MISS_TRT_LOCK> Check TRT state / hit_read = 0 / hit_write = 1 / wok = 1 / index = 1
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc0c / cpt = 9
****************** cycle 1701453 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp  invalid no error ins 0>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_WAIT | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_CAS_NLINE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc0c / WAY = 0 / SET = 1 / WORD = 9
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_CMD_CAS_NLINE> Send a put request to xram
  <MEMC memc_0_0.CAS_WAIT> Release all locks
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0xac000000 / cpt = 10
****************** cycle 1701454 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_CAS_NLINE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_CC_CHECK> paddr = 0x000018040 r_dcache_vci_paddr = 0x000018058 mask = 0x0ffffffc0 (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) = 0 (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT) = 0 ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) = 0x1
  <PROC proc_0_0_1 DCACHE_CC_CHECK> Coherence request received: PADDR = 0x000018040 / TYPE = 1 / HIT = 1
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 2885681152 / WAY = 0 / SET = 1 / WORD = 10
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_CMD_CAS_NLINE> Send a put request to xram
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc0d / cpt = 11
****************** cycle 1701455 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_CAS_NLINE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc0d / WAY = 0 / SET = 1 / WORD = 11
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_CMD_CAS_NLINE> Send a put request to xram
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x18058 / hit = 0 / count = 0 / is_cnt = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0xac000000 / cpt = 12
****************** cycle 1701456 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_MISS_TRT_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_CAS_NLINE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_CC_CHECK> paddr = 0x000018040 r_dcache_vci_paddr = 0x000019000 mask = 0x0ffffffc0 (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) = 0 (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT) = 0 ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) = 0
  <PROC proc_0_0_0 DCACHE_CC_CHECK> Coherence request received: PADDR = 0x000018040 / TYPE = 1 / HIT = 1
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 2885681152 / WAY = 0 / SET = 1 / WORD = 12
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_CMD_CAS_NLINE> Send a put request to xram
  <MEMC memc_0_0.CAS_MISS_TRT_LOCK> Check TRT state / hit_read = 0 / hit_write = 1 / wok = 1 / index = 1
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc0e / cpt = 13
****************** cycle 1701457 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_WAIT | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_CAS_NLINE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc0e / WAY = 0 / SET = 1 / WORD = 13
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_CMD_CAS_NLINE> Send a put request to xram
  <MEMC memc_0_0.CAS_WAIT> Release all locks
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 14
****************** cycle 1701458 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_DATA_MISS | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 1 / WORD = 14
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_RSP_IDLE> Response from XRAM to a put transaction
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 2 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 15
****************** cycle 1701459 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_DATA_UPDT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_ACK | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 1 / WORD = 15
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_RSP_ACK>
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x18058 / hit = 0 / count = 0 / is_cnt = 0
****************** cycle 1701460 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_DIR_UPDT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT | READ_IDLE | WRITE_IDLE | CAS_MISS_TRT_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_TRT_ERASE | XRAM_RSP_IDLE
  <PROC proc_0_0_0.DCACHE_INVAL_TLB_SCAN> Invalidate DTLB entry: line = 0x000000601 / set = 2 / way = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_CC_BROADCAST > Slot goes to ZOMBI state  SET = 1 / WAY = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_MISS_TRT_LOCK> Check TRT state / hit_read = 0 / hit_write = 1 / wok = 1 / index = 1
****************** cycle 1701461 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_CC_CHECK | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT | READ_IDLE | WRITE_IDLE | CAS_WAIT | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_TRT_ERASE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 DCACHE_CC_CHECK> paddr = 0x000018040 r_dcache_vci_paddr = 0x000018058 mask = 0x0ffffffc0 (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) = 0 (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT) = 0x1 ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) = 0x1
  <PROC proc_0_0_2 DCACHE_CC_CHECK> Coherence request matching a pending miss: PADDR = 0x000018040
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_WAIT> Release all locks
****************** cycle 1701462 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_MISS_DIR_UPDT | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_TRT_ERASE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0x1
  <PROC proc_0_0_2 DCACHE_MISS_DIR_UPDT> Switch slot to ZOMBI state PADDR = 0x000018058 / WAY = 0 / SET = 1
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 1
  <PROC proc_0_0_3 r_dcache_cc_send_nline = 0d1537
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_RSP_TRT_ERASE> Erase TRT entry 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.TGT_RSP_INIT> Write response after coherence transaction / rsrcid = 0 / rtrdid = 0 / rpktid = 5
****************** cycle 1701463 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_dcache_cc_send_nline = 0x000000601
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x18058 / hit = 0 / count = 0 / is_cnt = 0
****************** cycle 1701464 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_CLEANUP_1
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_MISS_TRT_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0.DCACHE_INVAL_TLB_SCAN> Invalidate DTLB entry: line = 0x000000601 / set = 6 / way = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_CC_BROADCAST > Slot goes to ZOMBI state  SET = 1 / WAY = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_dcache_cc_send_nline = 0d1537
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701465 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_CLEANUP_2
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_MISS_TRT_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_dcache_cc_send_nline = 0x000000601
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_MISS_TRT_LOCK> Check TRT state / hit_read = 0 / hit_write = 0 / wok = 0x1 / index = 0
****************** cycle 1701466 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_MISS_TRT_SET | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_CLEANUP | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_CC_BROADCAST > Slot goes to ZOMBI state  SET = 0x1 / WAY = 0x2
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_dcache_cc_send_nline = 0x000000601
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_MISS_TRT_SET> Register a GET transaction in TRT / nline = 0x601 / trt_index = 0
****************** cycle 1701467 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_MISS_XRAM_REQ | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_CLEANUP | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_dcache_cc_send_nline = 0x000000601
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CLEANUP_IDLE> Cleanup request: / owner_id = 0x3 / owner_ins = 0
  <MEMC memc_0_0.CAS_MISS_XRAM_REQ> Request a GET transaction to IXR_CMD FSM / nline = 0x601 / trt_index = 0
****************** cycle 1701468 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_WAIT | CLEANUP_GET_NLINE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_0 r_dcache_cc_send_nline = 0x000000601
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CLEANUP_GET_NLINE> Cleanup request: / address = 0x18040
  <MEMC memc_0_0.CAS_WAIT> Release all locks
****************** cycle 1701469 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_DIR_REQ
  CC_SEND_CAS_IDLE | CC_RECEIVE_CLEANUP | MULTI_ACK_IDLE | IXR_CMD_CAS_NLINE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_dcache_cc_send_nline = 0x000000601
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_CMD_CAS_NLINE> Send a get request to xram
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701470 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_DIR_REQ
  CC_SEND_CAS_IDLE | CC_RECEIVE_CLEANUP | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_RSP_IDLE> Response from XRAM to a get transaction
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x18058 / hit = 0 / count = 0 / is_cnt = 0
****************** cycle 1701471 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_MISS_TRT_LOCK | CLEANUP_DIR_REQ
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_MISS_TRT_LOCK> Check TRT state / hit_read = 0x1 / hit_write = 0 / wok = 0x1 / index = 0x1
****************** cycle 1701472 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_WAIT | CLEANUP_DIR_REQ
  CC_SEND_CAS_IDLE | CC_RECEIVE_CLEANUP | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <PROC proc_0_0_0.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x8000070c / BYPASS = 0x1 / PTE_ADR = 0x000019000
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CLEANUP_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.CAS_WAIT> Release all locks
****************** cycle 1701473 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_DIR_LOCK
  CC_SEND_CAS_IDLE | CC_RECEIVE_CLEANUP | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <PROC proc_0_0_0.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0xaa000000 PTE_PPN = 0x4
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 0 / data = 0x8c000000
  <MEMC memc_0_0.CLEANUP_DIR_LOCK> Test directory status:  line = 0x00000018040 / hit = 0 / dir_id = 0 / dir_ins = 0 / search_id = 0x3 / search_ins = 0 / count = 0 / is_cnt = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701474 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_UPT_LOCK
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 2 / set = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 1 / data = 0xbfc08
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701475 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_UPT_LOCK
  CC_SEND_CAS_IDLE | CC_RECEIVE_CLEANUP | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB / set = 0 / way = 2
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
     [0] [0]   [1][1][0][1][1][1][0][0][0][0][1][0x17f80][  0xbfc00][0x000000600]
     [0] [1]   [1][1][0][1][0][1][0][0][0][0][1][0x10012][      0xd][0x000000652]
     [0] [2]   [1][1][0][1][0][1][0][0][0][0][1][0x10000][      0x4][0x000000640]
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 2 / data = 0x8c000000
  <MEMC memc_0_0.CLEANUP_UPT_LOCK> Cleanup matching pending invalidate transaction on UPT: address = 0x18040 upt_entry = 0x1
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701476 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_UPT_DECREMENT
  CC_SEND_CAS_IDLE | CC_RECEIVE_CLEANUP | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 3 / data = 0xbfc09
  <MEMC memc_0_0.CLEANUP_UPT_DECREMENT> Decrement response counter in UPT: UPT_index = 0x1 rsp_count = 0x3
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x18058 / hit = 0 / count = 0 / is_cnt = 0
****************** cycle 1701477 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_MISS_TRT_LOCK | CLEANUP_SEND_ACK
  CC_SEND_CAS_IDLE | CC_RECEIVE_CLEANUP | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 4 / data = 0xac400000
  <MEMC memc_0_0.CLEANUP_SEND_ACK> Send the response to a cleanup request: srcid = 3
****************** cycle 1701478 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_MISS_TRT_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_CLEANUP | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 5 / data = 0xbfc0a
  <MEMC memc_0_0.CLEANUP_IDLE> Cleanup request: / owner_id = 0x2 / owner_ins = 0
****************** cycle 1701479 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_MISS_TRT_LOCK | CLEANUP_GET_NLINE
  CC_SEND_CLEANUP_ACK | CC_RECEIVE_CLEANUP | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <PROC proc_0_0_0 ICACHE_MISS_SELECT> Select a slot: / WAY = 0 / SET = 28 / VICTIM = 0x002ff009c
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 6 / data = 0xac000000
  <MEMC memc_0_0.CLEANUP_GET_NLINE> Cleanup request: / address = 0x18040
  <MEMC memc_0_0.CC_SEND_CLEANUP_ACK> Cleanup Acknowledgement for srcid 0x3
****************** cycle 1701480 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_MISS_TRT_LOCK | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_CLEANUP | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <PROC proc_0_0_0 ICACHE_MISS_CLEAN> Switch to ZOMBI state / WAY = 0 / SET = 28
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 7 / data = 0xbfc0b
****************** cycle 1701481 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_MISS_TRT_LOCK | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_dcache_cc_send_nline = 0x000000601
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d0 / for address 0x000004700
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 8 / data = 0xac000000
****************** cycle 1701482 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_READ | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_MISS_TRT_LOCK | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_dcache_cc_send_nline = 0x000000601
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_READ> Push into read_fifo: address = 0x000004700 srcid = 0d0 trdid = 0d0 pktid = 0d3 plen = 0d64
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 9 / data = 0xbfc0c
****************** cycle 1701483 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_MISS_TRT_LOCK | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_IDLE> Read request: srcid = 0 / address = 0x4700 / pktid = 0x3 / nwords = 16
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 10 / data = 0xac000000
****************** cycle 1701484 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_DIR_REQ | WRITE_IDLE | CAS_MISS_TRT_LOCK | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_CLEANUP | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_CC_CHECK> paddr = 0x000018040 r_dcache_vci_paddr = 0x000018058 mask = 0x0ffffffc0 (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) = 0 (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT) = 0 ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) = 0x1
  <PROC proc_0_0_3 DCACHE_CC_CHECK> CC_TYPE_CLACK Switch slot to EMPTY state set = 0x1 / way = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 11 / data = 0xbfc0d
****************** cycle 1701485 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_DIR_REQ | WRITE_IDLE | CAS_MISS_TRT_LOCK | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_CLEANUP | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 12 / data = 0xac000000
****************** cycle 1701486 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_DIR_REQ | WRITE_IDLE | CAS_MISS_TRT_LOCK | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_CLEANUP | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 13 / data = 0xbfc0e
****************** cycle 1701487 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_DIR_REQ | WRITE_IDLE | CAS_MISS_TRT_LOCK | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_CLEANUP | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 14 / data = 0
****************** cycle 1701488 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_DIR_REQ | WRITE_IDLE | CAS_MISS_TRT_LOCK | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_CLEANUP | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 15 / data = 0
****************** cycle 1701489 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_DIR_REQ | WRITE_IDLE | CAS_MISS_TRT_LOCK | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_CLEANUP | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.XRAM_RSP_IDLE> Available cache line in TRT: index = 0
****************** cycle 1701490 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_DIR_REQ | WRITE_IDLE | CAS_MISS_TRT_LOCK | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_CLEANUP | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.CAS_MISS_TRT_LOCK> Check TRT state / hit_read = 0x1 / hit_write = 0 / wok = 0x1 / index = 0x1
****************** cycle 1701491 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_DIR_REQ | WRITE_IDLE | CAS_WAIT | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_CLEANUP | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.CLEANUP_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.CAS_WAIT> Release all locks
****************** cycle 1701492 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_DIR_REQ | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_DIR_LOCK
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_CLEANUP | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.CLEANUP_DIR_LOCK> Test directory status:  line = 0x00000018040 / hit = 0 / dir_id = 0 / dir_ins = 0 / search_id = 0x2 / search_ins = 0 / count = 0 / is_cnt = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701493 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_DIR_REQ | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_UPT_LOCK
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_CLEANUP | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.CLEANUP_UPT_LOCK> Cleanup matching pending invalidate transaction on UPT: address = 0x18040 upt_entry = 0x1
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701494 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_DIR_REQ | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_UPT_DECREMENT
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_CLEANUP | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.CLEANUP_UPT_DECREMENT> Decrement response counter in UPT: UPT_index = 0x1 rsp_count = 0x2
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701495 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_DIR_REQ | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_SEND_ACK
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_CLEANUP | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.XRAM_RSP_DIR_LOCK> Get access to directory
  <MEMC memc_0_0.CLEANUP_SEND_ACK> Send the response to a cleanup request: srcid = 2
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701496 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_DIR_REQ | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_CLEANUP | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_IDLE | XRAM_RSP_TRT_COPY
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.XRAM_RSP_TRT_COPY> Select a slot:  way = 0 / set = 1 / inval_required = 0
  <MEMC memc_0_0.CLEANUP_IDLE> Cleanup request: / owner_id = 0x1 / owner_ins = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701497 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_DIR_REQ | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_GET_NLINE
  CC_SEND_CLEANUP_ACK | CC_RECEIVE_CLEANUP | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_IDLE | XRAM_RSP_INVAL_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.CLEANUP_GET_NLINE> Cleanup request: / address = 0x18040
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.CC_SEND_CLEANUP_ACK> Cleanup Acknowledgement for srcid 0x2
****************** cycle 1701498 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_DIR_REQ | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_CLEANUP | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_IDLE | XRAM_RSP_INVAL_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.XRAM_RSP_INVAL_LOCK> Get acces to UPT, but an invalidation is already registered at this address
UPDATE TAB ENTRY 0--------
valid  = 0
update = 1
brdcast= 0
rsp    = 1
srcid  = 0
trdid  = 0
pktid  = 5
nline  = 0x00000000640
count  = 0
UPDATE TAB ENTRY 1--------
valid  = 1
update = 0
brdcast= 1
rsp    = 1
srcid  = 3
trdid  = 0
pktid  = 5
nline  = 0x00000000601
count  = 2
UPDATE TAB ENTRY 2--------
valid  = 0
update = 0
brdcast= 0
rsp    = 0
srcid  = 0
trdid  = 0
pktid  = 0
nline  = 0x00000000000
count  = 0
UPDATE TAB ENTRY 3--------
valid  = 0
update = 0
brdcast= 0
rsp    = 0
srcid  = 0
trdid  = 0
pktid  = 0
nline  = 0x00000000000
count  = 0
UPDATE TAB ENTRY 4--------
valid  = 0
update = 0
brdcast= 0
rsp    = 0
srcid  = 0
trdid  = 0
pktid  = 0
nline  = 0x00000000000
count  = 0
UPDATE TAB ENTRY 5--------
valid  = 0
update = 0
brdcast= 0
rsp    = 0
srcid  = 0
trdid  = 0
pktid  = 0
nline  = 0x00000000000
count  = 0
UPDATE TAB ENTRY 6--------
valid  = 0
update = 0
brdcast= 0
rsp    = 0
srcid  = 0
trdid  = 0
pktid  = 0
nline  = 0x00000000000
count  = 0
UPDATE TAB ENTRY 7--------
valid  = 0
update = 0
brdcast= 0
rsp    = 0
srcid  = 0
trdid  = 0
pktid  = 0
nline  = 0x00000000000
count  = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701499 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_DIR_REQ | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_IDLE | XRAM_RSP_INVAL_WAIT
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701500 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_CLACK | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_DIR_REQ | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701501 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_DIR_LOCK | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_LOCK> Accessing directory:  address = 0x4700 / hit = 0 / count = 0 / is_cnt = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701502 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_TRT_LOCK | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701503 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_TRT_LOCK | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_TRT_LOCK> Check TRT: hit_read = 0 / hit_write = 0 / full = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701504 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_TRT_SET | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_TRT_SET> Write in Transaction Table:  address = 0x4700 / srcid = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701505 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_TRT_REQ | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_TRT_REQ> Request GET transaction for address 0x4700
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x18058 / hit = 0 / count = 0 / is_cnt = 0
****************** cycle 1701506 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_MISS_TRT_LOCK | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_CAS_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701507 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_MISS_TRT_LOCK | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_NLINE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_CMD_READ_NLINE> Send a get request to xram
  <MEMC memc_0_0.CAS_MISS_TRT_LOCK> Check TRT state / hit_read = 0x1 / hit_write = 0 / wok = 0x1 / index = 0x2
****************** cycle 1701508 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_WAIT | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_RSP_IDLE> Response from XRAM to a get transaction
  <MEMC memc_0_0.CLEANUP_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.CAS_WAIT> Release all locks
****************** cycle 1701509 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_DIR_LOCK
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CLEANUP_DIR_LOCK> Test directory status:  line = 0x00000018040 / hit = 0 / dir_id = 0 / dir_ins = 0 / search_id = 0x1 / search_ins = 0 / count = 0 / is_cnt = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701510 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_UPT_LOCK
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 1 / word = 0 / data = 0x27bd0028
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701511 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_UPT_LOCK
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 1 / word = 1 / data = 0x3e00008
  <MEMC memc_0_0.CLEANUP_UPT_LOCK> Cleanup matching pending invalidate transaction on UPT: address = 0x18040 upt_entry = 0x1
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701512 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_UPT_DECREMENT
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 1 / word = 2 / data = 0
  <MEMC memc_0_0.CLEANUP_UPT_DECREMENT> Decrement response counter in UPT: UPT_index = 0x1 rsp_count = 0x1
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701513 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_SEND_ACK
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 1 / word = 3 / data = 0x27bdfff0
  <MEMC memc_0_0.CLEANUP_SEND_ACK> Send the response to a cleanup request: srcid = 1
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701514 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 1 / word = 4 / data = 0xafbe000c
  <MEMC memc_0_0.CLEANUP_IDLE> Cleanup request: / owner_id = 0 / owner_ins = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701515 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_GET_NLINE
  CC_SEND_CLEANUP_ACK | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 1 / word = 5 / data = 0x3a0f021
  <MEMC memc_0_0.CLEANUP_GET_NLINE> Cleanup request: / address = 0x18040
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.CC_SEND_CLEANUP_ACK> Cleanup Acknowledgement for srcid 0x1
****************** cycle 1701516 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 1 / word = 6 / data = 0x40027801
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701517 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 1 / word = 7 / data = 0xafc20000
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701518 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 1 / word = 8 / data = 0x8fc20000
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701519 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 1 / word = 9 / data = 0x30420fff
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701520 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_CC_CHECK> paddr = 0x000018040 r_dcache_vci_paddr = 0x000018058 mask = 0x0ffffffc0 (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) = 0 (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT) = 0 ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) = 0x1
  <PROC proc_0_0_1 DCACHE_CC_CHECK> CC_TYPE_CLACK Switch slot to EMPTY state set = 0x1 / way = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 1 / word = 10 / data = 0x3c0e821
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701521 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 1 / word = 11 / data = 0x8fbe000c
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701522 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 1 / word = 12 / data = 0x3e00008
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701523 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 1 / word = 13 / data = 0x27bd0010
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701524 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 1 / word = 14 / data = 0x27bdfff0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701525 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 1 / word = 15 / data = 0xafbe000c
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701526 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701527 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.XRAM_RSP_DIR_LOCK> Get access to directory
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701528 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_TRT_COPY
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.XRAM_RSP_TRT_COPY> Select a slot:  way = 0 / set = 1 / inval_required = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701529 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_INVAL_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701530 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_INVAL_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.XRAM_RSP_INVAL_LOCK> Get acces to UPT, but an invalidation is already registered at this address
UPDATE TAB ENTRY 0--------
valid  = 0
update = 1
brdcast= 0
rsp    = 1
srcid  = 0
trdid  = 0
pktid  = 5
nline  = 0x00000000640
count  = 0
UPDATE TAB ENTRY 1--------
valid  = 1
update = 0
brdcast= 1
rsp    = 1
srcid  = 3
trdid  = 0
pktid  = 5
nline  = 0x00000000601
count  = 1
UPDATE TAB ENTRY 2--------
valid  = 0
update = 0
brdcast= 0
rsp    = 0
srcid  = 0
trdid  = 0
pktid  = 0
nline  = 0x00000000000
count  = 0
UPDATE TAB ENTRY 3--------
valid  = 0
update = 0
brdcast= 0
rsp    = 0
srcid  = 0
trdid  = 0
pktid  = 0
nline  = 0x00000000000
count  = 0
UPDATE TAB ENTRY 4--------
valid  = 0
update = 0
brdcast= 0
rsp    = 0
srcid  = 0
trdid  = 0
pktid  = 0
nline  = 0x00000000000
count  = 0
UPDATE TAB ENTRY 5--------
valid  = 0
update = 0
brdcast= 0
rsp    = 0
srcid  = 0
trdid  = 0
pktid  = 0
nline  = 0x00000000000
count  = 0
UPDATE TAB ENTRY 6--------
valid  = 0
update = 0
brdcast= 0
rsp    = 0
srcid  = 0
trdid  = 0
pktid  = 0
nline  = 0x00000000000
count  = 0
UPDATE TAB ENTRY 7--------
valid  = 0
update = 0
brdcast= 0
rsp    = 0
srcid  = 0
trdid  = 0
pktid  = 0
nline  = 0x00000000000
count  = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701531 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_INVAL_WAIT
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701532 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701533 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x18058 / hit = 0 / count = 0 / is_cnt = 0
****************** cycle 1701534 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_MISS_TRT_LOCK | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701535 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_MISS_TRT_LOCK | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_MISS_TRT_LOCK> Check TRT state / hit_read = 0x1 / hit_write = 0 / wok = 0x1 / index = 0x2
****************** cycle 1701536 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_WAIT | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CLEANUP_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.CAS_WAIT> Release all locks
****************** cycle 1701537 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_DIR_LOCK
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CLEANUP_DIR_LOCK> Test directory status:  line = 0x00000018040 / hit = 0 / dir_id = 0 / dir_ins = 0 / search_id = 0 / search_ins = 0 / count = 0 / is_cnt = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701538 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_UPT_LOCK
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701539 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_UPT_LOCK
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CLEANUP_UPT_LOCK> Cleanup matching pending invalidate transaction on UPT: address = 0x18040 upt_entry = 0x1
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701540 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_UPT_DECREMENT
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.XRAM_RSP_DIR_LOCK> Get access to directory
  <MEMC memc_0_0.CLEANUP_UPT_DECREMENT> Decrement response counter in UPT: UPT_index = 0x1 rsp_count = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701541 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_UPT_CLEAR
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_TRT_COPY
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.XRAM_RSP_TRT_COPY> Select a slot:  way = 0 / set = 1 / inval_required = 0
  <MEMC memc_0_0.CLEANUP_UPT_CLEAR> Clear entry in UPT: UPT_index = 1
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701542 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_WRITE_RSP
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_INVAL_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CLEANUP_WRITE_RSP> Send a response to a previous write request waiting for coherence transaction completion:  rsrcid = 3 / rtrdid = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701543 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_SEND_ACK
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_INVAL_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.XRAM_RSP_INVAL_LOCK> Get acces to UPT
  <MEMC memc_0_0.CLEANUP_SEND_ACK> Send the response to a cleanup request: srcid = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701544 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CLEANUP | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_UPDT
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.XRAM_RSP_DIR_UPDT> Directory update:  way = 0 / set = 1 / owner_id = 0 / owner_ins = 0 / count = 0 / is_cnt = 0
  <MEMC memc_0_0.CLEANUP_IDLE> Cleanup request: / owner_id = 0 / owner_ins = 0x1
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701545 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CLEANUP | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_GET_NLINE
  CC_SEND_CLEANUP_ACK | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.XRAM_RSP_IDLE> Available cache line in TRT: index = 1
  <MEMC memc_0_0.CLEANUP_GET_NLINE> Cleanup request: / address = 0xbfc02700
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.CC_SEND_CLEANUP_ACK> Cleanup Acknowledgement for srcid 0
****************** cycle 1701546 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CLEANUP | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x18058 / hit = 1 / count = 0 / is_cnt = 0
  <MEMC memc_0_0.TGT_RSP_CLEANUP> Cleanup response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1701547 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CLEANUP_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1701548 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CLEANUP_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8c000000 / actual value = 0xac000000 / forced_fail = 0
****************** cycle 1701549 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CLEANUP_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1701550 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CLEANUP_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_DIR_REQ
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 DCACHE_CC_CHECK> paddr = 0x000018040 r_dcache_vci_paddr = 0x000019000 mask = 0x0ffffffc0 (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) = 0 (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT) = 0 ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) = 0
  <PROC proc_0_0_0 DCACHE_CC_CHECK> CC_TYPE_CLACK Switch slot to EMPTY state set = 0x1 / way = 0x2
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> DTLB miss / VADDR = 0xbfc0b3fc / BYPASS = 0x1 / PTE_ADR = 0x000018058
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CLEANUP_DIR_REQ> Requesting DIR lock 
****************** cycle 1701551 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_DIR_LOCK
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_GET> MISS in dcache: PTE address = 0x000018058
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CLEANUP_DIR_LOCK> Test directory status:  line = 0x000bfc02700 / hit = 0 / dir_id = 0 / dir_ins = 0 / search_id = 0 / search_ins = 0x1 / count = 0 / is_cnt = 0
****************** cycle 1701552 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_UPT_LOCK
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_SELECT> Select a slot: / WAY = 0 / SET = 1 / PADDR = 0x000018058
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701553 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_UPT_LOCK
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.XRAM_RSP_DIR_LOCK> Get access to directory
  <MEMC memc_0_0.CLEANUP_UPT_LOCK> Unexpected cleanup with no corresponding UPT entry: address = 0xbfc02700
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 1 / rtrdid = 0 / rpktid = 5
****************** cycle 1701554 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_SEND_ACK
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_TRT_COPY
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000018040
  <MEMC memc_0_0.XRAM_RSP_TRT_COPY> Select a slot:  way = 1 / set = 28 / inval_required = 0
  <MEMC memc_0_0.CLEANUP_SEND_ACK> Send the response to a cleanup request: srcid = 0
****************** cycle 1701555 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_READ | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_INVAL_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_READ> Push into read_fifo: address = 0x000018040 srcid = 0d3 trdid = 0d0 pktid = 0d1 plen = 0d64
****************** cycle 1701556 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_ACK | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_INVAL_LOCK
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_IDLE> Read request: srcid = 3 / address = 0x18040 / pktid = 0x1 / nwords = 16
  <MEMC memc_0_0.XRAM_RSP_INVAL_LOCK> Get acces to UPT
  <MEMC memc_0_0.CC_SEND_CLEANUP_ACK> Cleanup Acknowledgement for srcid 0
****************** cycle 1701557 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_DIR_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_UPDT
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1.DCACHE_TLB_MISS> DTLB miss / VADDR = 0xbfc0b1fc / BYPASS = 0x1 / PTE_ADR = 0x000018058
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.XRAM_RSP_DIR_UPDT> Directory update:  way = 1 / set = 28 / owner_id = 0 / owner_ins = 1 / count = 1 / is_cnt = 0
****************** cycle 1701558 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_DIR_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_RSP
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_TLB_PTE2_GET> MISS in dcache: PTE address = 0x000018058
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.XRAM_RSP_DIR_RSP> Request the TGT_RSP FSM to return data: rsrcid = 0 / address = 0x4700 / nwords = 16
****************** cycle 1701559 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_DIR_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 DCACHE_MISS_SELECT> Select a slot: / WAY = 0 / SET = 1 / PADDR = 0x000018058
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_LOCK> Accessing directory:  address = 0x18040 / hit = 1 / count = 0 / is_cnt = 0
****************** cycle 1701560 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_DIR_HIT | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_HIT> Update directory entry: addr = 0x18040 / set = 1 / way = 0 / owner_id = 3 / owner_ins = 0 / count = 1 / is_cnt = 0
****************** cycle 1701561 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 ICACHE_CC_CHECK>  CC_TYPE_CLACK slot returns to empty state set = 0x1c / way = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d1 / for address 0x000018040
  <MEMC memc_0_0.READ_RSP> Request the TGT_RSP FSM to return data: rsrcid = 3 / address = 0x18040 / nwords = 16
****************** cycle 1701562 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_READ | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_READ> Push into read_fifo: address = 0x000018040 srcid = 0d1 trdid = 0d0 pktid = 0d1 plen = 0d64
  <MEMC memc_0_0.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0 / rpktid = 3 / rdata = 0x27bd0028 / cpt = 0
****************** cycle 1701563 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_IDLE> Read request: srcid = 1 / address = 0x18040 / pktid = 0x1 / nwords = 16
  <MEMC memc_0_0.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0 / rpktid = 3 / rdata = 0x3e00008 / cpt = 1
****************** cycle 1701564 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_DIR_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x27bd0028 WAY = 0 SET = 0x1c WORD = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
****************** cycle 1701565 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_DIR_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x3e00008 WAY = 0 SET = 0x1c WORD = 0x1
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_LOCK> Accessing directory:  address = 0x18040 / hit = 1 / count = 1 / is_cnt = 0
  <MEMC memc_0_0.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0 / rpktid = 3 / rdata = 0 / cpt = 2
****************** cycle 1701566 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_HEAP_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0 WAY = 0 SET = 0x1c WORD = 0x2
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_REQ> Requesting HEAP lock 
  <MEMC memc_0_0.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0 / rpktid = 3 / rdata = 0x27bdfff0 / cpt = 3
****************** cycle 1701567 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_HEAP_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x27bdfff0 WAY = 0 SET = 0x1c WORD = 0x3
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_LOCK> Update directory: tag = 0x6 set = 1 way = 0 count = 2 is_cnt = 0
  <MEMC memc_0_0.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0 / rpktid = 3 / rdata = 0xafbe000c / cpt = 4
****************** cycle 1701568 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_HEAP_WRITE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xafbe000c WAY = 0 SET = 0x1c WORD = 0x4
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_WRITE> Add an entry in the heap: owner_id = 0x1 owner_ins = 0
  <MEMC memc_0_0.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0 / rpktid = 3 / rdata = 0x3a0f021 / cpt = 5
****************** cycle 1701569 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x3a0f021 WAY = 0 SET = 0x1c WORD = 0x5
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0 / rpktid = 3 / rdata = 0x40027801 / cpt = 6
****************** cycle 1701570 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x40027801 WAY = 0 SET = 0x1c WORD = 0x6
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0 / rpktid = 3 / rdata = 0xafc20000 / cpt = 7
****************** cycle 1701571 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xafc20000 WAY = 0 SET = 0x1c WORD = 0x7
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0 / rpktid = 3 / rdata = 0x8fc20000 / cpt = 8
****************** cycle 1701572 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x8fc20000 WAY = 0 SET = 0x1c WORD = 0x8
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0 / rpktid = 3 / rdata = 0x30420fff / cpt = 9
****************** cycle 1701573 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x30420fff WAY = 0 SET = 0x1c WORD = 0x9
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0 / rpktid = 3 / rdata = 0x3c0e821 / cpt = 10
****************** cycle 1701574 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x3c0e821 WAY = 0 SET = 0x1c WORD = 0xa
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0 / rpktid = 3 / rdata = 0x8fbe000c / cpt = 11
****************** cycle 1701575 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x8fbe000c WAY = 0 SET = 0x1c WORD = 0xb
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0 / rpktid = 3 / rdata = 0x3e00008 / cpt = 12
****************** cycle 1701576 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x3e00008 WAY = 0 SET = 0x1c WORD = 0xc
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0 / rpktid = 3 / rdata = 0x27bd0010 / cpt = 13
****************** cycle 1701577 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x27bd0010 WAY = 0 SET = 0x1c WORD = 0xd
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0 / rpktid = 3 / rdata = 0x27bdfff0 / cpt = 14
****************** cycle 1701578 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x27bdfff0 WAY = 0 SET = 0x1c WORD = 0xe
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0 / rpktid = 3 / rdata = 0xafbe000c / cpt = 15
****************** cycle 1701579 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xafbe000c WAY = 0 SET = 0x1c WORD = 0xf
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701580 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 ICACHE_MISS_DIR_UPDT> Switch cache slot to VALID state PADDR = 0x00000470c WAY = 0 SET = 28
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701581 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701582 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0x8c000000 / cpt = 0
****************** cycle 1701583 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc08 / cpt = 1
****************** cycle 1701584 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0.DCACHE_TLB_MISS> DTLB miss / VADDR = 0xbfc0af94 / BYPASS = 0x1 / PTE_ADR = 0x000018050
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x8c000000 / WAY = 0 / SET = 1 / WORD = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701585 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_TLB_PTE2_GET> MISS in dcache: PTE address = 0x000018050
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc08 / WAY = 0 / SET = 1 / WORD = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0x8c000000 / cpt = 2
****************** cycle 1701586 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_MISS_SELECT> Select a slot: / WAY = 2 / SET = 1 / PADDR = 0x000018050
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x8c000000 / WAY = 0 / SET = 1 / WORD = 2
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc09 / cpt = 3
****************** cycle 1701587 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc09 / WAY = 0 / SET = 1 / WORD = 3
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0xac400000 / cpt = 4
****************** cycle 1701588 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xac400000 / WAY = 0 / SET = 1 / WORD = 4
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d0 / for address 0x000018040
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc0a / cpt = 5
****************** cycle 1701589 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_READ | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc0a / WAY = 0 / SET = 1 / WORD = 5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_READ> Push into read_fifo: address = 0x000018040 srcid = 0d0 trdid = 0d0 pktid = 0d1 plen = 0d64
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0xac000000 / cpt = 6
****************** cycle 1701590 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xac000000 / WAY = 0 / SET = 1 / WORD = 6
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc0b / cpt = 7
****************** cycle 1701591 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc0b / WAY = 0 / SET = 1 / WORD = 7
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0xac000000 / cpt = 8
****************** cycle 1701592 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xac000000 / WAY = 0 / SET = 1 / WORD = 8
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc0c / cpt = 9
****************** cycle 1701593 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc0c / WAY = 0 / SET = 1 / WORD = 9
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0xac000000 / cpt = 10
****************** cycle 1701594 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xac000000 / WAY = 0 / SET = 1 / WORD = 10
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc0d / cpt = 11
****************** cycle 1701595 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc0d / WAY = 0 / SET = 1 / WORD = 11
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0xac000000 / cpt = 12
****************** cycle 1701596 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xac000000 / WAY = 0 / SET = 1 / WORD = 12
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc0e / cpt = 13
****************** cycle 1701597 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc0e / WAY = 0 / SET = 1 / WORD = 13
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 14
****************** cycle 1701598 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 1 / WORD = 14
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 15
****************** cycle 1701599 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 1 / WORD = 15
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_RSP> Request the TGT_RSP FSM to return data: rsrcid = 1 / address = 0x18040 / nwords = 16
****************** cycle 1701600 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DIR_UPDT> Switch slot to VALID state PADDR = 0x000018058 / WAY = 0 / SET = 1
1 | way 0 | set 0 | @ 0xbfc0c000 | 0xbabef00d | 0x1 | 0x1 | 0x1 | 0xf | 0x4 | 0 | 0 | 0 | 0 | 0xb | 0x24 | 0x25 | 0x7 | 0x4 | 0x1c
1 | way 0 | set 1 | @ 0x18040 | 0x8c000000 | 0xbfc08 | 0x8c000000 | 0xbfc09 | 0xac400000 | 0xbfc0a | 0xac000000 | 0xbfc0b | 0xac000000 | 0xbfc0c | 0xac000000 | 0xbfc0d | 0xac000000 | 0xbfc0e | 0 | 0
0 | way 0 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 18 | @ 0x19480 | 0xaa000000 | 0xd | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 31 | @ 0x137c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xc0000018 | 0xc000001a
0 | way 0 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 62 | @ 0xbfc04f80 | 0x3000 | 0x12000 | 0x68000 | 0x8e000 | 0xb4000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 0 | @ 0x18000 | 0xae000000 | 0xbfc00 | 0x8e000000 | 0xbfc01 | 0x8e000000 | 0xbfc02 | 0xae000000 | 0xbfc03 | 0xae400000 | 0xbfc04 | 0x8e000000 | 0xbfc05 | 0 | 0 | 0 | 0
0 | way 1 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 0 | @ 0x13000 | 0xc0000019 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 0 | @ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_IDLE> Read request: srcid = 0 / address = 0x18040 / pktid = 0x1 / nwords = 16
****************** cycle 1701601 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0xac000000 PTE_PPN = 0xbfc0b
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
****************** cycle 1701602 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB: way = 0 / set = 3
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_LOCK> Accessing directory:  address = 0x18040 / hit = 1 / count = 2 / is_cnt = 0
****************** cycle 1701603 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB / set = 3 / way = 0
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
     [3] [0]   [1][1][0][1][1][0][0][0][0][0][1][0x17f81][  0xbfc0b][0x000000601]
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_REQ> Requesting HEAP lock 
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0x8c000000 / cpt = 0
****************** cycle 1701604 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_LOCK> Update directory: tag = 0x6 set = 1 way = 0 count = 3 is_cnt = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc08 / cpt = 1
****************** cycle 1701605 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_WRITE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x8c000000 / WAY = 0 / SET = 1 / WORD = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_WRITE> Add an entry in the heap: owner_id = 0 owner_ins = 0
****************** cycle 1701606 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc08 / WAY = 0 / SET = 1 / WORD = 1
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_DIRTY_GET_PTE> CAS request / PTE_PADDR = 0x000018058 / PTE_VALUE = 0xac000000 / SET = 1 / WAY = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0x8c000000 / cpt = 2
****************** cycle 1701607 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x8c000000 / WAY = 0 / SET = 1 / WORD = 2
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc09 / cpt = 3
****************** cycle 1701608 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc09 / WAY = 0 / SET = 1 / WORD = 3
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0xac400000 / cpt = 4
****************** cycle 1701609 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xac400000 / WAY = 0 / SET = 1 / WORD = 4
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000018058
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc0a / cpt = 5
****************** cycle 1701610 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc0a / WAY = 0 / SET = 1 / WORD = 5
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000018058 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0ac000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0xac000000 / cpt = 6
****************** cycle 1701611 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xac000000 / WAY = 0 / SET = 1 / WORD = 6
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000018058 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0ac400000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x18058 wdata = 0xac000000 eop = 0 cpt  = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc0b / cpt = 7
****************** cycle 1701612 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc0b / WAY = 0 / SET = 1 / WORD = 7
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x18058 wdata = 0xac400000 eop = 1 cpt  = 1
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0xac000000 / cpt = 8
****************** cycle 1701613 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xac000000 / WAY = 0 / SET = 1 / WORD = 8
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc0c / cpt = 9
****************** cycle 1701614 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc0c / WAY = 0 / SET = 1 / WORD = 9
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0xac000000 / cpt = 10
****************** cycle 1701615 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xac000000 / WAY = 0 / SET = 1 / WORD = 10
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x18058 / hit = 1 / count = 3 / is_cnt = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc0d / cpt = 11
****************** cycle 1701616 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc0d / WAY = 0 / SET = 1 / WORD = 11
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0xac000000 / cpt = 12
****************** cycle 1701617 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xac000000 / WAY = 0 / SET = 1 / WORD = 12
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 2885681152 / actual value = 2885681152 / forced_fail = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc0e / cpt = 13
****************** cycle 1701618 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_DIR_HIT_WRITE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc0e / WAY = 0 / SET = 1 / WORD = 13
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 14
****************** cycle 1701619 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_UPT_LOCK | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 1 / WORD = 14
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 15
****************** cycle 1701620 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_RSP | WRITE_IDLE | CAS_UPT_LOCK | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 1 / WORD = 15
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_RSP> Request the TGT_RSP FSM to return data: rsrcid = 0 / address = 0x18040 / nwords = 16
  <MEMC memc_0_0.CAS_UPT_LOCK> Register multi-update transaction in UPT / wok = 1 / nline  = 0x00000000601 / count = 0x3
****************** cycle 1701621 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_UPT_HEAP_LOCK | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DIR_UPDT> Switch slot to VALID state PADDR = 0x000018058 / WAY = 0 / SET = 1
1 | way 0 | set 0 | @ 0xbfc0c000 | 0xbabef00d | 0x1 | 0x1 | 0x1 | 0xf | 0x4 | 0 | 0 | 0 | 0 | 0xb | 0x24 | 0x25 | 0x7 | 0x4 | 0x1c
1 | way 0 | set 1 | @ 0x18040 | 0x8c000000 | 0xbfc08 | 0x8c000000 | 0xbfc09 | 0xac400000 | 0xbfc0a | 0xac000000 | 0xbfc0b | 0xac000000 | 0xbfc0c | 0xac000000 | 0xbfc0d | 0xac000000 | 0xbfc0e | 0 | 0
0 | way 0 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 18 | @ 0x19480 | 0xaa000000 | 0xd | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 31 | @ 0x137c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xc0000018 | 0xc000001a
0 | way 0 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 61 | @ 0xbfc04f40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x1000 | 0x2000
1 | way 0 | set 62 | @ 0xbfc04f80 | 0x3000 | 0x12000 | 0x68000 | 0x8e000 | 0xb4000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 0 | @ 0x18000 | 0xae000000 | 0xbfc00 | 0x8e000000 | 0xbfc01 | 0x8e000000 | 0xbfc02 | 0xae000000 | 0xbfc03 | 0xae400000 | 0xbfc04 | 0x8e000000 | 0xbfc05 | 0 | 0 | 0 | 0
0 | way 1 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 0 | @ 0x13000 | 0xc0000019 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 0 | @ 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701622 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_UPT_HEAP_LOCK | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0xac000000 PTE_PPN = 0xbfc0b
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_UPT_HEAP_LOCK> Get access to the heap
****************** cycle 1701623 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_UPT_REQ | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB: way = 0 / set = 3
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_UPT_REQ> Send the first update request to CC_SEND FSM  / address = 0x18058 / wdata = 0xac400000 / srcid = 3 / inst = 0
****************** cycle 1701624 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_UPT_NEXT | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB / set = 3 / way = 0
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
     [3] [0]   [1][1][0][1][1][0][0][0][0][0][1][0x17f81][  0xbfc0b][0x000000601]
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_UPT_NEXT> Send the next update request to CC_SEND FSM  / address = 0x18058 / wdata = 0xac400000 / srcid = 0 / inst = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0x8c000000 / cpt = 0
****************** cycle 1701625 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_UPT_NEXT | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_HEADER | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_UPT_NEXT> Send the next update request to CC_SEND FSM  / address = 0x18058 / wdata = 0xac400000 / srcid = 1 / inst = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc08 / cpt = 1
****************** cycle 1701626 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x8c000000 / WAY = 2 / SET = 1 / WORD = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CC_SEND_CAS_UPDT_NLINE> Multicast-Update for line 0d1537
****************** cycle 1701627 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_DATA | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc08 / WAY = 2 / SET = 1 / WORD = 1
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_DIRTY_GET_PTE> CAS request / PTE_PADDR = 0x000018058 / PTE_VALUE = 0xac000000 / SET = 1 / WAY = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0x8c000000 / cpt = 2
****************** cycle 1701628 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_HEADER | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x8c000000 / WAY = 2 / SET = 1 / WORD = 2
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc09 / cpt = 3
****************** cycle 1701629 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc09 / WAY = 2 / SET = 1 / WORD = 3
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0xac400000 / cpt = 4
****************** cycle 1701630 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xac400000 / WAY = 2 / SET = 1 / WORD = 4
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d1 / for address 0x000018058
  <MEMC memc_0_0.CC_SEND_CAS_UPDT_NLINE> Multicast-Update for line 0x00000000601
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc0a / cpt = 5
****************** cycle 1701631 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_DATA | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc0a / WAY = 2 / SET = 1 / WORD = 5
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000018058 srcid = 0d1 trdid = 0d0 pktid = 0d5 wdata = 0x0ac000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0xac000000 / cpt = 6
****************** cycle 1701632 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_HEADER | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xac000000 / WAY = 2 / SET = 1 / WORD = 6
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_CC_CHECK> paddr = 0d98368 r_dcache_vci_paddr = 0d98392 mask = 0d4294967232 (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) = 0 (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT) = 0 ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) = 1
  <PROC proc_0_0_3 DCACHE_CC_CHECK> Coherence request received: PADDR = 0x000018040 / TYPE = 3 / HIT = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000018058 srcid = 0d1 trdid = 0d0 pktid = 0d5 wdata = 0x0ac400000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 1 addr = 0x18058 wdata = 0xac000000 eop = 0 cpt  = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc0b / cpt = 7
****************** cycle 1701633 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc0b / WAY = 2 / SET = 1 / WORD = 7
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 1 addr = 0x18058 wdata = 0xac400000 eop = 1 cpt  = 1
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0xac000000 / cpt = 8
****************** cycle 1701634 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xac000000 / WAY = 2 / SET = 1 / WORD = 8
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.CC_SEND_CAS_UPDT_NLINE> Multicast-Update for line 0d1537
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc0c / cpt = 9
****************** cycle 1701635 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_DATA | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc0c / WAY = 2 / SET = 1 / WORD = 9
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x18058 / hit = 1 / count = 3 / is_cnt = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0xac000000 / cpt = 10
****************** cycle 1701636 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_HEADER | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xac000000 / WAY = 2 / SET = 1 / WORD = 10
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc0d / cpt = 11
****************** cycle 1701637 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc0d / WAY = 2 / SET = 1 / WORD = 11
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_INVAL_TLB_SCAN> Invalidate DTLB entry: line = 0x000000601 / set = 3 / way = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 2885681152 / actual value = 2889875456 / forced_fail = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0xac000000 / cpt = 12
****************** cycle 1701638 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xac000000 / WAY = 2 / SET = 1 / WORD = 12
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0xbfc0e / cpt = 13
****************** cycle 1701639 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc0e / WAY = 2 / SET = 1 / WORD = 13
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 14
****************** cycle 1701640 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 1 / WORD = 14
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_CC_CHECK> paddr = 0d98368 r_dcache_vci_paddr = 0d98392 mask = 0d4294967232 (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) = 0 (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT) = 0 ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) = 1
  <PROC proc_0_0_1 DCACHE_CC_CHECK> Coherence request received: PADDR = 0x000018040 / TYPE = 3 / HIT = 1
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 0 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 15
****************** cycle 1701641 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 2 / SET = 1 / WORD = 15
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701642 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_CC_UPDT> Write one word / WAY = 0 / SET = 1 / WORD = 6 / VALUE = 0xac400000
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701643 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 DCACHE_CC_CHECK> paddr = 0x000018040 r_dcache_vci_paddr = 0x000018050 mask = 0x0ffffffc0 (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) = 0 (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT) = 0x1 ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) = 0x1
  <PROC proc_0_0_0 DCACHE_CC_CHECK> Coherence request matching a pending miss: PADDR = 0x000018040
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701644 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0x1
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 1 / rtrdid = 0 / rpktid = 5
****************** cycle 1701645 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0x1
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0x1
  <PROC proc_0_0_1.DCACHE_INVAL_TLB_SCAN> Invalidate DTLB entry: line = 0x000000601 / set = 3 / way = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701646 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0x1
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0x1
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701647 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0x1
  <PROC proc_0_0_0 DCACHE_MISS_DIR_UPDT> Switch slot to ZOMBI state PADDR = 0x000018050 / WAY = 2 / SET = 1
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 1
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701648 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_MULTI_ACK | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701649 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_dcache_cc_send_nline = 0x000000601
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.MULTI_ACK_IDLE> Response for UPT entry 
****************** cycle 1701650 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_MULTI_ACK | MULTI_ACK_UPT_LOCK | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_dcache_cc_send_nline = 0x000000601
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_CC_UPDT> Write one word / WAY = 0 / SET = 1 / WORD = 6 / VALUE = 0xac400000
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701651 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_UPT_LOCK | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_DIRTY_WAIT> CAS completed
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.MULTI_ACK_UPT_LOCK> Decrement the responses counter for UPT: entry = 0 / rsp_count = 2
****************** cycle 1701652 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_CLEANUP | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.MULTI_ACK_IDLE> Response for UPT entry 
****************** cycle 1701653 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_CLEANUP | MULTI_ACK_UPT_LOCK | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1.DCACHE_TLB_MISS> DTLB miss / VADDR = 0xbfc0b1fc / BYPASS = 0x1 / PTE_ADR = 0x000018058
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.MULTI_ACK_UPT_LOCK> Decrement the responses counter for UPT: entry = 0 / rsp_count = 1
  <MEMC memc_0_0.CLEANUP_IDLE> Cleanup request: / owner_id = 0 / owner_ins = 0
****************** cycle 1701654 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_GET_NLINE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0xac400000 PTE_PPN = 0xbfc0b
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CLEANUP_GET_NLINE> Cleanup request: / address = 0x18040
****************** cycle 1701655 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_DIR_REQ
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB: way = 0 / set = 3
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701656 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_DIR_REQ
  CC_SEND_CAS_IDLE | CC_RECEIVE_MULTI_ACK | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB / set = 3 / way = 0
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
     [3] [0]   [1][1][0][1][1][0][0][0][1][0][1][0x17f81][  0xbfc0b][0x000000601]
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CLEANUP_DIR_REQ> Requesting DIR lock 
****************** cycle 1701657 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_DIR_LOCK
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.MULTI_ACK_IDLE> Response for UPT entry 
  <MEMC memc_0_0.CLEANUP_DIR_LOCK> Test directory status:  line = 0x00000018040 / hit = 0x1 / dir_id = 0x3 / dir_ins = 0 / search_id = 0 / search_ins = 0 / count = 0x3 / is_cnt = 0
****************** cycle 1701658 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_HEAP_REQ
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_UPT_LOCK | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.MULTI_ACK_UPT_LOCK> Decrement the responses counter for UPT: entry = 0 / rsp_count = 0
****************** cycle 1701659 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_HEAP_REQ
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_UPT_CLEAR | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.MULTI_ACK_UPT_CLEAR> Clear UPT entry 0
  <MEMC memc_0_0.CLEANUP_HEAP_REQ> HEAP lock acquired 
****************** cycle 1701660 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_HEAP_LOCK
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_WRITE_RSP | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.MULTI_ACK_WRITE_RSP> Request TGT_RSP FSM to send a response to srcid 0x3
  <MEMC memc_0_0.CLEANUP_HEAP_LOCK> Checks matching: address = 0x18040 / dir_id = 0x3 / dir_ins = 0 / heap_id = 0 / heap_ins = 0 / search_id = 0 / search_ins = 0
****************** cycle 1701661 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_HEAP_FREE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CLEANUP_HEAP_SEARCH> Update the list of free entries
****************** cycle 1701662 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_SEND_ACK
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CLEANUP_SEND_ACK> Send the response to a cleanup request: srcid = 0
****************** cycle 1701663 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701664 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_ACK | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x8000070c / BYPASS = 0x1 / PTE_ADR = 0x000019000
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CC_SEND_CLEANUP_ACK> Cleanup Acknowledgement for srcid 0
  <MEMC memc_0_0.TGT_RSP_INIT> Write response after coherence transaction / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1701665 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_TLB_PTE2_GET> MISS in dcache: PTE address = 0x000019000
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_DIRTY_WAIT> CAS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701666 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_SELECT> Select a slot: / WAY = 3 / SET = 0 / PADDR = 0x000019000
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701667 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> DTLB miss / VADDR = 0xbfc0b3fc / BYPASS = 0x1 / PTE_ADR = 0x000018058
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701668 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0xac400000 PTE_PPN = 0xbfc0b
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d1 / for address 0x000019000
****************** cycle 1701669 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_READ | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB: way = 0 / set = 3
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_READ> Push into read_fifo: address = 0x000019000 srcid = 0d1 trdid = 0d0 pktid = 0d1 plen = 0d64
****************** cycle 1701670 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB / set = 3 / way = 0
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
     [3] [0]   [1][1][0][1][1][0][0][0][1][0][1][0x17f81][  0xbfc0b][0x000000601]
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_IDLE> Read request: srcid = 1 / address = 0x19000 / pktid = 0x1 / nwords = 16
****************** cycle 1701671 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_DIR_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
****************** cycle 1701672 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_DIR_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
****************** cycle 1701673 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_DIR_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_LOCK> Accessing directory:  address = 0x19000 / hit = 1 / count = 1 / is_cnt = 0
****************** cycle 1701674 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_HEAP_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_REQ> Requesting HEAP lock 
****************** cycle 1701675 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_HEAP_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_REQ> Requesting HEAP lock 
****************** cycle 1701676 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_HEAP_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_LOCK> Update directory: tag = 0x6 set = 64 way = 1 count = 2 is_cnt = 0
****************** cycle 1701677 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_HEAP_WRITE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_WRITE> Add an entry in the heap: owner_id = 0x1 owner_ins = 0
****************** cycle 1701678 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x8000070c / BYPASS = 0x1 / PTE_ADR = 0x000019000
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_RSP> Request the TGT_RSP FSM to return data: rsrcid = 1 / address = 0x19000 / nwords = 16
****************** cycle 1701679 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_INIT_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_GET> MISS in dcache: PTE address = 0x000019000
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701680 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_SELECT> Select a slot: / WAY = 3 / SET = 0 / PADDR = 0x000019000
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701681 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701682 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0xaa000000 / cpt = 0
****************** cycle 1701683 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0x4 / cpt = 1
****************** cycle 1701684 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xaa000000 / WAY = 3 / SET = 0 / WORD = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019000
****************** cycle 1701685 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_READ | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x4 / WAY = 3 / SET = 0 / WORD = 1
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_READ> Push into read_fifo: address = 0x000019000 srcid = 0d3 trdid = 0d0 pktid = 0d1 plen = 0d64
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0x8a000000 / cpt = 2
****************** cycle 1701686 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x8a000000 / WAY = 3 / SET = 0 / WORD = 2
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_IDLE> Read request: srcid = 3 / address = 0x19000 / pktid = 0x1 / nwords = 16
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0x5 / cpt = 3
****************** cycle 1701687 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x5 / WAY = 3 / SET = 0 / WORD = 3
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0x8a000000 / cpt = 4
****************** cycle 1701688 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x8a000000 / WAY = 3 / SET = 0 / WORD = 4
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_LOCK> Accessing directory:  address = 0x19000 / hit = 1 / count = 2 / is_cnt = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0x6 / cpt = 5
****************** cycle 1701689 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x6 / WAY = 3 / SET = 0 / WORD = 5
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_REQ> Requesting HEAP lock 
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0x8a000000 / cpt = 6
****************** cycle 1701690 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x8a000000 / WAY = 3 / SET = 0 / WORD = 6
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_LOCK> Update directory: tag = 0x6 set = 64 way = 1 count = 3 is_cnt = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0x7 / cpt = 7
****************** cycle 1701691 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_WRITE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x7 / WAY = 3 / SET = 0 / WORD = 7
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_WRITE> Add an entry in the heap: owner_id = 3 owner_ins = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 8
****************** cycle 1701692 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 3 / SET = 0 / WORD = 8
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 9
****************** cycle 1701693 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 3 / SET = 0 / WORD = 9
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 10
****************** cycle 1701694 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 3 / SET = 0 / WORD = 10
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 11
****************** cycle 1701695 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 3 / SET = 0 / WORD = 11
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 12
****************** cycle 1701696 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 3 / SET = 0 / WORD = 12
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 13
****************** cycle 1701697 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 3 / SET = 0 / WORD = 13
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 14
****************** cycle 1701698 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 3 / SET = 0 / WORD = 14
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 15
****************** cycle 1701699 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 3 / SET = 0 / WORD = 15
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_RSP> Request the TGT_RSP FSM to return data: rsrcid = 3 / address = 0x19000 / nwords = 16
****************** cycle 1701700 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DIR_UPDT> Switch slot to VALID state PADDR = 0x000019000 / WAY = 3 / SET = 0
1 | way 0 | set 0 | @ 0xbfc0c000 | 0xbabef00d | 0x1 | 0x1 | 0x1 | 0xf | 0x4 | 0 | 0 | 0 | 0 | 0xb | 0x24 | 0x25 | 0x7 | 0x4 | 0x1c
1 | way 0 | set 1 | @ 0x18040 | 0x8c000000 | 0xbfc08 | 0x8c000000 | 0xbfc09 | 0xac400000 | 0xbfc0a | 0xac400000 | 0xbfc0b | 0xac000000 | 0xbfc0c | 0xac000000 | 0xbfc0d | 0xac000000 | 0xbfc0e | 0 | 0
0 | way 0 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 18 | @ 0x19480 | 0xaa000000 | 0xd | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 31 | @ 0x137c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xc0000018 | 0xc000001a
0 | way 0 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 61 | @ 0xbfc04f40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x1000 | 0x2000
1 | way 0 | set 62 | @ 0xbfc04f80 | 0x3000 | 0x12000 | 0x68000 | 0x8e000 | 0xb4000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 0 | @ 0x18000 | 0xae000000 | 0xbfc00 | 0x8e000000 | 0xbfc01 | 0x8e000000 | 0xbfc02 | 0xae000000 | 0xbfc03 | 0xae400000 | 0xbfc04 | 0x8e000000 | 0xbfc05 | 0 | 0 | 0 | 0
0 | way 1 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 0 | @ 0x13000 | 0xc0000019 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 3 | set 0 | @ 0x19000 | 0xaa000000 | 0x4 | 0x8a000000 | 0x5 | 0x8a000000 | 0x6 | 0x8a000000 | 0x7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701701 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0xaa000000 PTE_PPN = 0x4
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701702 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 2 / set = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701703 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB / set = 0 / way = 2
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
     [0] [0]   [1][1][0][1][1][1][0][0][0][0][1][0x17f80][  0xbfc00][0x000000600]
     [0] [1]   [1][1][0][1][0][1][0][0][0][0][1][0x10012][      0xd][0x000000652]
     [0] [2]   [1][1][0][1][0][1][0][0][0][0][1][0x10000][      0x4][0x000000640]
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0xaa000000 / cpt = 0
****************** cycle 1701704 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0x4 / cpt = 1
****************** cycle 1701705 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xaa000000 / WAY = 3 / SET = 0 / WORD = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701706 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x4 / WAY = 3 / SET = 0 / WORD = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0x8a000000 / cpt = 2
****************** cycle 1701707 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 ICACHE_MISS_SELECT> Select a slot: / WAY = 0 / SET = 28
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 2315255808 / WAY = 3 / SET = 0 / WORD = 2
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0x5 / cpt = 3
****************** cycle 1701708 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x5 / WAY = 3 / SET = 0 / WORD = 3
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0x8a000000 / cpt = 4
****************** cycle 1701709 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x8a000000 / WAY = 3 / SET = 0 / WORD = 4
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d1 / for address 0x000004700
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0x6 / cpt = 5
****************** cycle 1701710 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_READ | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x6 / WAY = 3 / SET = 0 / WORD = 5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_READ> Push into read_fifo: address = 0x000004700 srcid = 0d1 trdid = 0d0 pktid = 0d3 plen = 0d64
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0x8a000000 / cpt = 6
****************** cycle 1701711 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x8a000000 / WAY = 3 / SET = 0 / WORD = 6
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_IDLE> Read request: srcid = 1 / address = 0x4700 / pktid = 0x3 / nwords = 16
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0x7 / cpt = 7
****************** cycle 1701712 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x7 / WAY = 3 / SET = 0 / WORD = 7
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 8
****************** cycle 1701713 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 3 / SET = 0 / WORD = 8
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_LOCK> Accessing directory:  address = 0x4700 / hit = 1 / count = 1 / is_cnt = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 9
****************** cycle 1701714 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 3 / SET = 0 / WORD = 9
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_REQ> Requesting HEAP lock 
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 10
****************** cycle 1701715 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 3 / SET = 0 / WORD = 10
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_LOCK> Update directory: tag = 0x1 set = 28 way = 1 count = 2 is_cnt = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 11
****************** cycle 1701716 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_WRITE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 3 / SET = 0 / WORD = 11
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_WRITE> Add an entry in the heap: owner_id = 1 owner_ins = 1
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 12
****************** cycle 1701717 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 3 / SET = 0 / WORD = 12
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 13
****************** cycle 1701718 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 3 / SET = 0 / WORD = 13
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 14
****************** cycle 1701719 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 3 / SET = 0 / WORD = 14
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 1 / rdata = 0 / cpt = 15
****************** cycle 1701720 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 3 / SET = 0 / WORD = 15
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_RSP> Request the TGT_RSP FSM to return data: rsrcid = 1 / address = 0x4700 / nwords = 16
****************** cycle 1701721 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DIR_UPDT> Switch slot to VALID state PADDR = 0x000019000 / WAY = 3 / SET = 0
1 | way 0 | set 0 | @ 0xbfc0c000 | 0xbabef00d | 0x1 | 0x1 | 0x1 | 0xf | 0x4 | 0 | 0 | 0 | 0 | 0xb | 0x24 | 0x25 | 0x7 | 0x4 | 0x1c
1 | way 0 | set 1 | @ 0x18040 | 0x8c000000 | 0xbfc08 | 0x8c000000 | 0xbfc09 | 0xac400000 | 0xbfc0a | 0xac400000 | 0xbfc0b | 0xac000000 | 0xbfc0c | 0xac000000 | 0xbfc0d | 0xac000000 | 0xbfc0e | 0 | 0
0 | way 0 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 18 | @ 0x19480 | 0xaa000000 | 0xd | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 31 | @ 0x137c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xc0000018 | 0xc000001a
0 | way 0 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 62 | @ 0xbfc04f80 | 0x3000 | 0x12000 | 0x68000 | 0x8e000 | 0xb4000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 0 | @ 0x18000 | 0xae000000 | 0xbfc00 | 0x8e000000 | 0xbfc01 | 0x8e000000 | 0xbfc02 | 0xae000000 | 0xbfc03 | 0xae400000 | 0xbfc04 | 0x8e000000 | 0xbfc05 | 0 | 0 | 0 | 0
0 | way 1 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 0 | @ 0x13000 | 0xc0000019 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 3 | set 0 | @ 0x19000 | 0xaa000000 | 0x4 | 0x8a000000 | 0x5 | 0x8a000000 | 0x6 | 0x8a000000 | 0x7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701722 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0xaa000000 PTE_PPN = 0x4
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701723 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 2 / set = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701724 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB / set = 0 / way = 2
     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
     [0] [0]   [1][1][0][1][1][1][0][0][0][0][1][0x17f80][  0xbfc00][0x000000600]
     [0] [1]   [1][1][0][1][0][1][0][0][0][0][1][0x10012][      0xd][0x000000652]
     [0] [2]   [1][1][0][1][0][1][0][0][0][0][1][0x10000][      0x4][0x000000640]
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 3 / rdata = 0x27bd0028 / cpt = 0
****************** cycle 1701725 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 3 / rdata = 0x3e00008 / cpt = 1
****************** cycle 1701726 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x27bd0028 WAY = 0 SET = 0x1c WORD = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701727 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x3e00008 WAY = 0 SET = 0x1c WORD = 0x1
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 3 / rdata = 0 / cpt = 2
****************** cycle 1701728 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0 WAY = 0 SET = 0x1c WORD = 0x2
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 ICACHE_MISS_SELECT> Select a slot: / WAY = 0 / SET = 28
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 3 / rdata = 0x27bdfff0 / cpt = 3
****************** cycle 1701729 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x27bdfff0 WAY = 0 SET = 0x1c WORD = 0x3
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 3 / rdata = 0xafbe000c / cpt = 4
****************** cycle 1701730 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xafbe000c WAY = 0 SET = 0x1c WORD = 0x4
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000004700
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 3 / rdata = 0x3a0f021 / cpt = 5
****************** cycle 1701731 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_READ | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x3a0f021 WAY = 0 SET = 0x1c WORD = 0x5
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_READ> Push into read_fifo: address = 0x000004700 srcid = 0d3 trdid = 0d0 pktid = 0d3 plen = 0d64
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 3 / rdata = 0x40027801 / cpt = 6
****************** cycle 1701732 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x40027801 WAY = 0 SET = 0x1c WORD = 0x6
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_IDLE> Read request: srcid = 3 / address = 0x4700 / pktid = 0x3 / nwords = 16
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 3 / rdata = 0xafc20000 / cpt = 7
****************** cycle 1701733 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xafc20000 WAY = 0 SET = 0x1c WORD = 0x7
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_REQ> Requesting DIR lock 
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 3 / rdata = 0x8fc20000 / cpt = 8
****************** cycle 1701734 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_DIR_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x8fc20000 WAY = 0 SET = 0x1c WORD = 0x8
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_DIR_LOCK> Accessing directory:  address = 0x4700 / hit = 1 / count = 2 / is_cnt = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 3 / rdata = 0x30420fff / cpt = 9
****************** cycle 1701735 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_REQ | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x30420fff WAY = 0 SET = 0x1c WORD = 0x9
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_REQ> Requesting HEAP lock 
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 3 / rdata = 0x3c0e821 / cpt = 10
****************** cycle 1701736 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_LOCK | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x3c0e821 WAY = 0 SET = 0x1c WORD = 0xa
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_LOCK> Update directory: tag = 0x1 set = 28 way = 1 count = 3 is_cnt = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 3 / rdata = 0x8fbe000c / cpt = 11
****************** cycle 1701737 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_HEAP_WRITE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x8fbe000c WAY = 0 SET = 0x1c WORD = 0xb
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_HEAP_WRITE> Add an entry in the heap: owner_id = 0x3 owner_ins = 0x1
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 3 / rdata = 0x3e00008 / cpt = 12
****************** cycle 1701738 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x3e00008 WAY = 0 SET = 0x1c WORD = 0xc
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 3 / rdata = 0x27bd0010 / cpt = 13
****************** cycle 1701739 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x27bd0010 WAY = 0 SET = 0x1c WORD = 0xd
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 3 / rdata = 0x27bdfff0 / cpt = 14
****************** cycle 1701740 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x27bdfff0 WAY = 0 SET = 0x1c WORD = 0xe
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 1 / rtrdid = 0 / rpktid = 3 / rdata = 0xafbe000c / cpt = 15
****************** cycle 1701741 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_RSP | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xafbe000c WAY = 0 SET = 0x1c WORD = 0xf
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.READ_RSP> Request the TGT_RSP FSM to return data: rsrcid = 3 / address = 0x4700 / nwords = 16
****************** cycle 1701742 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 ICACHE_MISS_DIR_UPDT> Switch cache slot to VALID state PADDR = 0x00000470c WAY = 0 SET = 28
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701743 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701744 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701745 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 3 / rdata = 0x27bd0028 / cpt = 0
****************** cycle 1701746 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 3 / rdata = 0x3e00008 / cpt = 1
****************** cycle 1701747 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x27bd0028 WAY = 0 SET = 0x1c WORD = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701748 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x3e00008 WAY = 0 SET = 0x1c WORD = 0x1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 3 / rdata = 0 / cpt = 2
****************** cycle 1701749 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1.DCACHE_IDLE> READ MISS in dcache
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0 WAY = 0 SET = 0x1c WORD = 0x2
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 3 / rdata = 0x27bdfff0 / cpt = 3
****************** cycle 1701750 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_SELECT> Select a slot: / WAY = 0 / SET = 6 / PADDR = 0x0bfc0b188
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x27bdfff0 WAY = 0 SET = 0x1c WORD = 0x3
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 3 / rdata = 0xafbe000c / cpt = 4
****************** cycle 1701751 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xafbe000c WAY = 0 SET = 0x1c WORD = 0x4
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 3 / rdata = 0x3a0f021 / cpt = 5
****************** cycle 1701752 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x3a0f021 WAY = 0 SET = 0x1c WORD = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 3 / rdata = 0x40027801 / cpt = 6
****************** cycle 1701753 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x40027801 WAY = 0 SET = 0x1c WORD = 0x6
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 3 / rdata = 0xafc20000 / cpt = 7
****************** cycle 1701754 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xafc20000 WAY = 0 SET = 0x1c WORD = 0x7
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 3 / rdata = 0x8fc20000 / cpt = 8
****************** cycle 1701755 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x8fc20000 WAY = 0 SET = 0x1c WORD = 0x8
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 3 / rdata = 0x30420fff / cpt = 9
****************** cycle 1701756 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x30420fff WAY = 0 SET = 0x1c WORD = 0x9
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 3 / rdata = 0x3c0e821 / cpt = 10
****************** cycle 1701757 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x3c0e821 WAY = 0 SET = 0x1c WORD = 0xa
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 3 / rdata = 0x8fbe000c / cpt = 11
****************** cycle 1701758 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x8fbe000c WAY = 0 SET = 0x1c WORD = 0xb
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 3 / rdata = 0x3e00008 / cpt = 12
****************** cycle 1701759 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x3e00008 WAY = 0 SET = 0x1c WORD = 0xc
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 3 / rdata = 0x27bd0010 / cpt = 13
****************** cycle 1701760 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x27bd0010 WAY = 0 SET = 0x1c WORD = 0xd
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 3 / rdata = 0x27bdfff0 / cpt = 14
****************** cycle 1701761 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0x27bdfff0 WAY = 0 SET = 0x1c WORD = 0xe
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_READ> Read response / rsrcid = 3 / rtrdid = 0 / rpktid = 3 / rdata = 0xafbe000c / cpt = 15
****************** cycle 1701762 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 ICACHE_MISS_DATA_UPDT> Write one word: WDATA = 0xafbe000c WAY = 0 SET = 0x1c WORD = 0xf
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701763 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 ICACHE_MISS_DIR_UPDT> Switch cache slot to VALID state PADDR = 0x00000470c WAY = 0 SET = 28
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701764 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701765 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701766 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701767 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 6 / WORD = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701768 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 6 / WORD = 1
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701769 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x80000001 / WAY = 0 / SET = 6 / WORD = 2
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701770 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 6 / WORD = 3
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_IDLE> READ MISS in dcache
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701771 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 6 / WORD = 4
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_SELECT> Select a slot: / WAY = 0 / SET = 14 / PADDR = 0x0bfc0b388
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701772 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc0b198 / WAY = 0 / SET = 6 / WORD = 5
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701773 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 6 / WORD = 6
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701774 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 6 / WORD = 7
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701775 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 6 / WORD = 8
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701776 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 6 / WORD = 9
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701777 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 6 / WORD = 10
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701778 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 6 / WORD = 11
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701779 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 6 / WORD = 12
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701780 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 6 / WORD = 13
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701781 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 6 / WORD = 14
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701782 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 6 / WORD = 15
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701783 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DIR_UPDT> Switch slot to VALID state PADDR = 0x0bfc0b188 / WAY = 0 / SET = 6
1 | way 0 | set 0 | @ 0xbfc0c000 | 0xbabef00d | 0x1 | 0x1 | 0x1 | 0xf | 0x4 | 0 | 0 | 0 | 0 | 0xb | 0x24 | 0x25 | 0x7 | 0x4 | 0x1c
1 | way 0 | set 1 | @ 0x18040 | 0x8c000000 | 0xbfc08 | 0x8c000000 | 0xbfc09 | 0xac400000 | 0xbfc0a | 0xac400000 | 0xbfc0b | 0xac000000 | 0xbfc0c | 0xac000000 | 0xbfc0d | 0xac000000 | 0xbfc0e | 0 | 0
0 | way 0 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 6 | @ 0xbfc0b180 | 0 | 0 | 0x80000001 | 0 | 0 | 0xbfc0b198 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 18 | @ 0x19480 | 0xaa000000 | 0xd | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 31 | @ 0x137c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xc0000018 | 0xc000001a
0 | way 0 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 61 | @ 0xbfc04f40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x1000 | 0x2000
1 | way 0 | set 62 | @ 0xbfc04f80 | 0x3000 | 0x12000 | 0x68000 | 0x8e000 | 0xb4000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 0 | @ 0x18000 | 0xae000000 | 0xbfc00 | 0x8e000000 | 0xbfc01 | 0x8e000000 | 0xbfc02 | 0xae000000 | 0xbfc03 | 0xae400000 | 0xbfc04 | 0x8e000000 | 0xbfc05 | 0 | 0 | 0 | 0
0 | way 1 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 0 | @ 0x13000 | 0xc0000019 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 3 | set 0 | @ 0x19000 | 0xaa000000 | 0x4 | 0x8a000000 | 0x5 | 0x8a000000 | 0x6 | 0x8a000000 | 0x7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701784 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1.DCACHE_IDLE> READ HIT in dcache
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701785 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701786 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701787 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701788 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1.DCACHE_IDLE> READ HIT in dcache
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701789 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701790 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701791 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701792 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1.DCACHE_IDLE> READ MISS in dcache
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701793 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_SELECT> Select a slot: / WAY = 0 / SET = 7 / PADDR = 0x0bfc0b1f4
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701794 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701795 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701796 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701797 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 14 / WORD = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701798 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 14 / WORD = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701799 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x80000003 / WAY = 0 / SET = 14 / WORD = 2
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701800 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 14 / WORD = 3
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701801 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 14 / WORD = 4
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701802 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0xbfc0b398 / WAY = 0 / SET = 14 / WORD = 5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701803 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 14 / WORD = 6
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701804 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 14 / WORD = 7
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701805 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 14 / WORD = 8
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701806 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 14 / WORD = 9
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701807 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 14 / WORD = 10
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701808 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 14 / WORD = 11
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701809 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 14 / WORD = 12
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701810 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 14 / WORD = 13
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701811 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 14 / WORD = 14
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701812 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 14 / WORD = 15
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701813 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DIR_UPDT> Switch slot to VALID state PADDR = 0x0bfc0b388 / WAY = 0 / SET = 14
1 | way 0 | set 0 | @ 0xbfc0c000 | 0xbabef00d | 0x1 | 0x1 | 0x1 | 0xf | 0x4 | 0 | 0 | 0 | 0 | 0xb | 0x24 | 0x25 | 0x7 | 0x4 | 0x1c
1 | way 0 | set 1 | @ 0x18040 | 0x8c000000 | 0xbfc08 | 0x8c000000 | 0xbfc09 | 0xac400000 | 0xbfc0a | 0xac400000 | 0xbfc0b | 0xac000000 | 0xbfc0c | 0xac000000 | 0xbfc0d | 0xac000000 | 0xbfc0e | 0 | 0
0 | way 0 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 14 | @ 0xbfc0b380 | 0 | 0 | 0x80000003 | 0 | 0 | 0xbfc0b398 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 18 | @ 0x19480 | 0xaa000000 | 0xd | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 31 | @ 0x137c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xc0000018 | 0xc000001a
0 | way 0 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 62 | @ 0xbfc04f80 | 0x3000 | 0x12000 | 0x68000 | 0x8e000 | 0xb4000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 0 | @ 0x18000 | 0xae000000 | 0xbfc00 | 0x8e000000 | 0xbfc01 | 0x8e000000 | 0xbfc02 | 0xae000000 | 0xbfc03 | 0xae400000 | 0xbfc04 | 0x8e000000 | 0xbfc05 | 0 | 0 | 0 | 0
0 | way 1 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 0 | @ 0x13000 | 0xc0000019 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 3 | set 0 | @ 0x19000 | 0xaa000000 | 0x4 | 0x8a000000 | 0x5 | 0x8a000000 | 0x6 | 0x8a000000 | 0x7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701814 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_IDLE> READ HIT in dcache
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701815 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701816 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701817 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701818 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_IDLE> READ HIT in dcache
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701819 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701820 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701821 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701822 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_IDLE> READ MISS in dcache
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701823 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 7 / WORD = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_SELECT> Select a slot: / WAY = 0 / SET = 15 / PADDR = 0x0bfc0b3f4
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701824 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 7 / WORD = 1
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701825 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 7 / WORD = 2
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701826 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 7 / WORD = 3
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701827 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 7 / WORD = 4
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701828 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 7 / WORD = 5
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701829 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 7 / WORD = 6
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701830 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 7 / WORD = 7
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701831 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 7 / WORD = 8
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701832 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 7 / WORD = 9
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701833 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 7 / WORD = 10
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701834 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 7 / WORD = 11
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701835 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 7 / WORD = 12
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701836 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x1 / WAY = 0 / SET = 7 / WORD = 13
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701837 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 7 / WORD = 14
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701838 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 7 / WORD = 15
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701839 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_MISS_DIR_UPDT> Switch slot to VALID state PADDR = 0x0bfc0b1f4 / WAY = 0 / SET = 7
1 | way 0 | set 0 | @ 0xbfc0c000 | 0xbabef00d | 0x1 | 0x1 | 0x1 | 0xf | 0x4 | 0 | 0 | 0 | 0 | 0xb | 0x24 | 0x25 | 0x7 | 0x4 | 0x1c
1 | way 0 | set 1 | @ 0x18040 | 0x8c000000 | 0xbfc08 | 0x8c000000 | 0xbfc09 | 0xac400000 | 0xbfc0a | 0xac400000 | 0xbfc0b | 0xac000000 | 0xbfc0c | 0xac000000 | 0xbfc0d | 0xac000000 | 0xbfc0e | 0 | 0
0 | way 0 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 6 | @ 0xbfc0b180 | 0 | 0 | 0x80000001 | 0 | 0 | 0xbfc0b198 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 7 | @ 0xbfc0b1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x1 | 0 | 0
0 | way 0 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 18 | @ 0x19480 | 0xaa000000 | 0xd | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 31 | @ 0x137c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xc0000018 | 0xc000001a
0 | way 0 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 61 | @ 0xbfc04f40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x1000 | 0x2000
1 | way 0 | set 62 | @ 0xbfc04f80 | 0x3000 | 0x12000 | 0x68000 | 0x8e000 | 0xb4000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 0 | @ 0x18000 | 0xae000000 | 0xbfc00 | 0x8e000000 | 0xbfc01 | 0x8e000000 | 0xbfc02 | 0xae000000 | 0xbfc03 | 0xae400000 | 0xbfc04 | 0x8e000000 | 0xbfc05 | 0 | 0 | 0 | 0
0 | way 1 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 0 | @ 0x13000 | 0xc0000019 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 3 | set 0 | @ 0x19000 | 0xaa000000 | 0x4 | 0x8a000000 | 0x5 | 0x8a000000 | 0x6 | 0x8a000000 | 0x7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701840 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1.DCACHE_IDLE> READ HIT in dcache
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701841 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701842 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701843 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701844 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_IDLE> Cache update in P1 stage / WAY = 0 / SET = 7 / WORD = 12 / DATA = 0 / BE = 0x0f
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701845 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1.DCACHE_IDLE> READ HIT in dcache
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701846 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701847 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701848 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701849 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 15 / WORD = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701850 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_IDLE> Cache update in P1 stage / WAY = 0 / SET = 7 / WORD = 11 / DATA = 0x1 / BE = 0x0f
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 15 / WORD = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701851 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 15 / WORD = 2
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701852 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 15 / WORD = 3
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701853 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 15 / WORD = 4
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701854 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 15 / WORD = 5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701855 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 15 / WORD = 6
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701856 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 15 / WORD = 7
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701857 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 15 / WORD = 8
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701858 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 15 / WORD = 9
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701859 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 15 / WORD = 10
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701860 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 15 / WORD = 11
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701861 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 15 / WORD = 12
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701862 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0x3 / WAY = 0 / SET = 15 / WORD = 13
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701863 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 15 / WORD = 14
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701864 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DATA_UPDT> Write one word: / DATA = 0 / WAY = 0 / SET = 15 / WORD = 15
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701865 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_MISS_DIR_UPDT> Switch slot to VALID state PADDR = 0x0bfc0b3f4 / WAY = 0 / SET = 15
1 | way 0 | set 0 | @ 0xbfc0c000 | 0xbabef00d | 0x1 | 0x1 | 0x1 | 0xf | 0x4 | 0 | 0 | 0 | 0 | 0xb | 0x24 | 0x25 | 0x7 | 0x4 | 0x1c
1 | way 0 | set 1 | @ 0x18040 | 0x8c000000 | 0xbfc08 | 0x8c000000 | 0xbfc09 | 0xac400000 | 0xbfc0a | 0xac400000 | 0xbfc0b | 0xac000000 | 0xbfc0c | 0xac000000 | 0xbfc0d | 0xac000000 | 0xbfc0e | 0 | 0
0 | way 0 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 14 | @ 0xbfc0b380 | 0 | 0 | 0x80000003 | 0 | 0 | 0xbfc0b398 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 15 | @ 0xbfc0b3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0x3 | 0 | 0
0 | way 0 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 18 | @ 0x19480 | 0xaa000000 | 0xd | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 31 | @ 0x137c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0xc0000018 | 0xc000001a
0 | way 0 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 0 | set 62 | @ 0xbfc04f80 | 0x3000 | 0x12000 | 0x68000 | 0x8e000 | 0xb4000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 0 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 1 | set 0 | @ 0x18000 | 0xae000000 | 0xbfc00 | 0x8e000000 | 0xbfc01 | 0x8e000000 | 0xbfc02 | 0xae000000 | 0xbfc03 | 0xae400000 | 0xbfc04 | 0x8e000000 | 0xbfc05 | 0 | 0 | 0 | 0
0 | way 1 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 1 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 2 | set 0 | @ 0x13000 | 0xc0000019 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 2 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
1 | way 3 | set 0 | @ 0x19000 | 0xaa000000 | 0x4 | 0x8a000000 | 0x5 | 0x8a000000 | 0x6 | 0x8a000000 | 0x7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 1 | @ 0x40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 2 | @ 0x80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 3 | @ 0xc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 4 | @ 0x100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 5 | @ 0x140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 6 | @ 0x180 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 7 | @ 0x1c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 8 | @ 0x200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 9 | @ 0x240 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 10 | @ 0x280 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 11 | @ 0x2c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 12 | @ 0x300 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 13 | @ 0x340 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 14 | @ 0x380 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 15 | @ 0x3c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 16 | @ 0x400 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 17 | @ 0x440 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 18 | @ 0x480 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 19 | @ 0x4c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 20 | @ 0x500 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 21 | @ 0x540 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 22 | @ 0x580 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 23 | @ 0x5c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 24 | @ 0x600 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 25 | @ 0x640 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 26 | @ 0x680 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 27 | @ 0x6c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 28 | @ 0x700 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 29 | @ 0x740 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 30 | @ 0x780 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 31 | @ 0x7c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 32 | @ 0x800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 33 | @ 0x840 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 34 | @ 0x880 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 35 | @ 0x8c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 36 | @ 0x900 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 37 | @ 0x940 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 38 | @ 0x980 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 39 | @ 0x9c0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 40 | @ 0xa00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 41 | @ 0xa40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 42 | @ 0xa80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 43 | @ 0xac0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 44 | @ 0xb00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 45 | @ 0xb40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 46 | @ 0xb80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 47 | @ 0xbc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 48 | @ 0xc00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 49 | @ 0xc40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 50 | @ 0xc80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 51 | @ 0xcc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 52 | @ 0xd00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 53 | @ 0xd40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 54 | @ 0xd80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 55 | @ 0xdc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 56 | @ 0xe00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 57 | @ 0xe40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 58 | @ 0xe80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 59 | @ 0xec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 60 | @ 0xf00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 61 | @ 0xf40 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 62 | @ 0xf80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
0 | way 3 | set 63 | @ 0xfc0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701866 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_IDLE> READ HIT in dcache
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701867 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701868 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701869 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701870 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_IDLE> Cache update in P1 stage / WAY = 0 / SET = 15 / WORD = 12 / DATA = 0 / BE = 0x0f
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701871 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_IDLE> READ HIT in dcache
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d1 / for address 0x000019008
****************** cycle 1701872 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d1 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1701873 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d1 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 1 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1701874 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 1 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1701875 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701876 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_IDLE> Cache update in P1 stage / WAY = 0 / SET = 15 / WORD = 11 / DATA = 0x3 / BE = 0x0f
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701877 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1701878 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1701879 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 2315255808 / actual value = 2315255808 / forced_fail = 0
****************** cycle 1701880 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_WRITE | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701881 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_UPT_LOCK | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701882 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_UPT_LOCK | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_UPT_LOCK> Register multi-update transaction in UPT / wok = 0x1 / nline  = 0x00000000640 / count = 0x3
****************** cycle 1701883 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_UPT_HEAP_LOCK | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701884 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_UPT_HEAP_LOCK | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
  <MEMC memc_0_0.CAS_UPT_HEAP_LOCK> Get access to the heap
****************** cycle 1701885 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_UPT_REQ | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_UPT_REQ> Send the first update request to CC_SEND FSM  / address = 0x19008 / wdata = 0xaa000000 / srcid = 0 / inst = 0
****************** cycle 1701886 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_UPT_NEXT | CLEANUP_IDLE
  CC_SEND_CLEANUP_IDLE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_UPT_NEXT> Send the next update request to CC_SEND FSM  / address = 0x19008 / wdata = 0xaa000000 / srcid = 3 / inst = 0
****************** cycle 1701887 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_UPT_NEXT | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_HEADER | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_UPT_NEXT> Send the next update request to CC_SEND FSM  / address = 0x19008 / wdata = 0xaa000000 / srcid = 1 / inst = 0
****************** cycle 1701888 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
  <MEMC memc_0_0.CC_SEND_CAS_UPDT_NLINE> Multicast-Update for line 0d1600
****************** cycle 1701889 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_DATA | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_0 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_0 r_dcache_miss_inval = 0
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1701890 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_HEADER | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701891 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1701892 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1701893 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1701894 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1701895 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701896 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701897 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701898 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1701899 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701900 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701901 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701902 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701903 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701904 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701905 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701906 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701907 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701908 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701909 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701910 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701911 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1701912 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1701913 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1701914 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1701915 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701916 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1701917 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1701918 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1701919 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1701920 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701921 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701922 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701923 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1701924 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701925 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701926 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701927 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701928 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701929 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701930 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701931 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701932 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701933 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701934 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701935 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701936 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1701937 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1701938 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1701939 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1701940 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701941 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1701942 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1701943 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1701944 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1701945 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701946 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701947 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701948 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1701949 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701950 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701951 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701952 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701953 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701954 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701955 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701956 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701957 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701958 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701959 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701960 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701961 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1701962 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1701963 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1701964 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1701965 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701966 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1701967 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1701968 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1701969 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1701970 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701971 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701972 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701973 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1701974 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701975 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701976 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701977 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701978 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701979 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701980 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701981 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701982 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701983 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701984 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701985 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701986 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1701987 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1701988 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1701989 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1701990 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1701991 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1701992 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1701993 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1701994 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1701995 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701996 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701997 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1701998 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1701999 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702000 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702001 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702002 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702003 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702004 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702005 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702006 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702007 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702008 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702009 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702010 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702011 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1702012 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1702013 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1702014 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1702015 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1702016 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1702017 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1702018 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1702019 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1702020 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702021 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702022 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702023 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1702024 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702025 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702026 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702027 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702028 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702029 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702030 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702031 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702032 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702033 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702034 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702035 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702036 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1702037 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1702038 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1702039 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1702040 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1702041 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1702042 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1702043 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1702044 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1702045 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702046 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702047 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702048 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1702049 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702050 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702051 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702052 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702053 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702054 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702055 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702056 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702057 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702058 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702059 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702060 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702061 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1702062 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1702063 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1702064 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1702065 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1702066 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1702067 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1702068 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1702069 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1702070 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702071 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702072 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702073 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1702074 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702075 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702076 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702077 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702078 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702079 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702080 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702081 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702082 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702083 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702084 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702085 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702086 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1702087 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1702088 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1702089 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1702090 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1702091 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1702092 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1702093 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1702094 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1702095 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702096 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702097 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702098 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1702099 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702100 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702101 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702102 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702103 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702104 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702105 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702106 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702107 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702108 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702109 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702110 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702111 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1702112 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1702113 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1702114 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1702115 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1702116 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1702117 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1702118 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1702119 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1702120 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702121 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702122 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702123 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1702124 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702125 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702126 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702127 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702128 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702129 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702130 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702131 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702132 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702133 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702134 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702135 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702136 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1702137 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1702138 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1702139 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1702140 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1702141 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1702142 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1702143 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1702144 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1702145 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702146 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702147 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702148 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1702149 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702150 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702151 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702152 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702153 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702154 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702155 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702156 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702157 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702158 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702159 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702160 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702161 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1702162 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1702163 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1702164 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1702165 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1702166 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1702167 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1702168 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1702169 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1702170 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702171 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702172 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702173 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1702174 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702175 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702176 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702177 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702178 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702179 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702180 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702181 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702182 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702183 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702184 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702185 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702186 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1702187 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1702188 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1702189 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1702190 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1702191 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1702192 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1702193 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1702194 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1702195 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702196 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702197 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702198 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1702199 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702200 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702201 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702202 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702203 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702204 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702205 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702206 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702207 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702208 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702209 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702210 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702211 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1702212 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1702213 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1702214 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1702215 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1702216 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1702217 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1702218 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1702219 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1702220 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702221 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702222 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702223 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1702224 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702225 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702226 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702227 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702228 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702229 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702230 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702231 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702232 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702233 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702234 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702235 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702236 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1702237 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1702238 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1702239 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1702240 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1702241 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1702242 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1702243 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1702244 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1702245 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702246 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702247 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702248 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1702249 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702250 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702251 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702252 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702253 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702254 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702255 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702256 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702257 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702258 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702259 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702260 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702261 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1702262 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1702263 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1702264 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1702265 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1702266 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1702267 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1702268 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1702269 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1702270 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702271 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702272 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702273 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1702274 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702275 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702276 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702277 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702278 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702279 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702280 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702281 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702282 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702283 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702284 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702285 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702286 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1702287 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1702288 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1702289 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1702290 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1702291 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1702292 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1702293 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1702294 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1702295 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702296 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702297 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702298 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1702299 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702300 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702301 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702302 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702303 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702304 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702305 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702306 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702307 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702308 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702309 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702310 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702311 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1702312 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1702313 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1702314 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1702315 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1702316 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1702317 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1702318 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1702319 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1702320 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702321 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702322 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702323 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1702324 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702325 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702326 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702327 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702328 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702329 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702330 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702331 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702332 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702333 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702334 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702335 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702336 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1702337 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1702338 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1702339 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1702340 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1702341 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1702342 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1702343 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1702344 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1702345 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702346 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702347 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702348 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1702349 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702350 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702351 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702352 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702353 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702354 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702355 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702356 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702357 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702358 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702359 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702360 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702361 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1702362 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1702363 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1702364 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1702365 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1702366 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1702367 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1702368 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1702369 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1702370 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702371 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702372 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702373 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1702374 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702375 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702376 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702377 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702378 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702379 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702380 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702381 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702382 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702383 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702384 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702385 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702386 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1702387 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1702388 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1702389 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1702390 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1702391 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1702392 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1702393 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1702394 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1702395 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702396 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702397 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702398 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1702399 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702400 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702401 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702402 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702403 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702404 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702405 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702406 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702407 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702408 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702409 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702410 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702411 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1702412 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1702413 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1702414 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1702415 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1702416 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1702417 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1702418 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1702419 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1702420 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702421 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702422 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702423 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1702424 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702425 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702426 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702427 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702428 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702429 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702430 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702431 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702432 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702433 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702434 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702435 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702436 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1702437 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1702438 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1702439 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1702440 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1702441 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1702442 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1702443 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1702444 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1702445 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702446 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702447 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702448 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1702449 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702450 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702451 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702452 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702453 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702454 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702455 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702456 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702457 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702458 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702459 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702460 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702461 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1702462 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1702463 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1702464 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1702465 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1702466 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1702467 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1702468 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1702469 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1702470 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702471 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702472 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702473 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1702474 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702475 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702476 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702477 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702478 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702479 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702480 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702481 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702482 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702483 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702484 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702485 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702486 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1702487 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1702488 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1702489 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1702490 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1702491 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1702492 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1702493 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1702494 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1702495 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702496 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702497 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702498 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1702499 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702500 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702501 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702502 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702503 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702504 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702505 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702506 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702507 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702508 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702509 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702510 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702511 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1702512 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1702513 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1702514 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1702515 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1702516 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1702517 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1702518 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1702519 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1702520 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702521 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702522 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702523 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1702524 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702525 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702526 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702527 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702528 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702529 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702530 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702531 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702532 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702533 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702534 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702535 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702536 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1702537 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1702538 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1702539 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1702540 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1702541 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1702542 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1702543 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1702544 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1702545 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702546 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702547 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702548 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1702549 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702550 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702551 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702552 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702553 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702554 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702555 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702556 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702557 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702558 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702559 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702560 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702561 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1702562 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1702563 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1702564 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1702565 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1702566 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1702567 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1702568 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1702569 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1702570 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702571 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702572 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702573 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1702574 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702575 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702576 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702577 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702578 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702579 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702580 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702581 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702582 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702583 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702584 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702585 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702586 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1702587 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1702588 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1702589 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1702590 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1702591 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1702592 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1702593 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1702594 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1702595 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702596 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702597 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702598 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1702599 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702600 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702601 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702602 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702603 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702604 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702605 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702606 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702607 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702608 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702609 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702610 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702611 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1702612 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1702613 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1702614 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1702615 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1702616 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1702617 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1702618 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1702619 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1702620 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702621 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702622 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702623 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1702624 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702625 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702626 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702627 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702628 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702629 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702630 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702631 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702632 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702633 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702634 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702635 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702636 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1702637 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1702638 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1702639 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1702640 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1702641 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1702642 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1702643 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1702644 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1702645 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702646 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702647 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702648 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1702649 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702650 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702651 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702652 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702653 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702654 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702655 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702656 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702657 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702658 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702659 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702660 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702661 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1702662 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1702663 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1702664 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1702665 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1702666 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1702667 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1702668 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1702669 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1702670 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702671 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702672 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702673 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1702674 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702675 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702676 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702677 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702678 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702679 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702680 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702681 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702682 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702683 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702684 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702685 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702686 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1702687 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1702688 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1702689 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1702690 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1702691 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1702692 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1702693 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1702694 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1702695 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702696 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702697 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702698 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1702699 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702700 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702701 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702702 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702703 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702704 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702705 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702706 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702707 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702708 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702709 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702710 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702711 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1702712 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1702713 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1702714 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1702715 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1702716 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1702717 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1702718 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1702719 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1702720 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702721 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702722 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702723 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1702724 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702725 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702726 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702727 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702728 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702729 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702730 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702731 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702732 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702733 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702734 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702735 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702736 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1702737 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1702738 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1702739 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1702740 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1702741 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1702742 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1702743 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1702744 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1702745 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702746 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702747 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702748 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1702749 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702750 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702751 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702752 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702753 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702754 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702755 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702756 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702757 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702758 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702759 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702760 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702761 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1702762 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1702763 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1702764 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1702765 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1702766 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1702767 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1702768 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1702769 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1702770 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702771 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702772 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702773 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1702774 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702775 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702776 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702777 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702778 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702779 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702780 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702781 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702782 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702783 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702784 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702785 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702786 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1702787 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1702788 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1702789 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1702790 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1702791 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1702792 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1702793 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1702794 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1702795 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702796 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702797 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702798 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1702799 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702800 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702801 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702802 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702803 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702804 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702805 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702806 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702807 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702808 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702809 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702810 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702811 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1702812 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1702813 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1702814 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1702815 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1702816 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1702817 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1702818 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1702819 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1702820 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702821 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702822 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702823 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1702824 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702825 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702826 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702827 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702828 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702829 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702830 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702831 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702832 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702833 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702834 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702835 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702836 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1702837 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1702838 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1702839 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1702840 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1702841 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1702842 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1702843 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1702844 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1702845 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702846 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702847 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702848 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1702849 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702850 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702851 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702852 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702853 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702854 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702855 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702856 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702857 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702858 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702859 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702860 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702861 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1702862 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1702863 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1702864 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1702865 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1702866 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1702867 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1702868 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1702869 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1702870 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702871 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702872 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702873 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1702874 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702875 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702876 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702877 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702878 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702879 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702880 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702881 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702882 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702883 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702884 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702885 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702886 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1702887 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1702888 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1702889 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1702890 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1702891 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1702892 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1702893 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1702894 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1702895 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702896 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702897 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702898 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1702899 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702900 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702901 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702902 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702903 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702904 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702905 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702906 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702907 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702908 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702909 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702910 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702911 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1702912 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1702913 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1702914 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1702915 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1702916 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1702917 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1702918 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1702919 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1702920 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702921 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702922 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702923 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1702924 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702925 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702926 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702927 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702928 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702929 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702930 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702931 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702932 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702933 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702934 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702935 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702936 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1702937 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1702938 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1702939 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1702940 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1702941 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1702942 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1702943 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1702944 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1702945 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702946 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702947 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702948 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1702949 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702950 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702951 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702952 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702953 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702954 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702955 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702956 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702957 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702958 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702959 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702960 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702961 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1702962 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1702963 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1702964 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1702965 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1702966 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1702967 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1702968 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1702969 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1702970 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702971 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702972 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702973 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1702974 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702975 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702976 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702977 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702978 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702979 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702980 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702981 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702982 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702983 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702984 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702985 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702986 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1702987 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1702988 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1702989 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1702990 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1702991 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1702992 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1702993 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1702994 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1702995 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702996 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702997 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1702998 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1702999 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703000 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703001 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703002 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703003 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703004 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703005 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703006 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703007 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703008 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703009 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703010 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703011 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1703012 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1703013 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1703014 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1703015 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1703016 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1703017 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1703018 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1703019 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1703020 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703021 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703022 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703023 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1703024 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703025 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703026 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703027 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703028 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703029 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703030 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703031 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703032 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703033 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703034 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703035 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703036 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1703037 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1703038 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1703039 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1703040 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1703041 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1703042 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1703043 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1703044 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1703045 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703046 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703047 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703048 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1703049 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703050 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703051 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703052 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703053 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703054 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703055 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703056 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703057 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703058 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703059 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703060 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703061 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1703062 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1703063 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1703064 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1703065 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1703066 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1703067 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1703068 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1703069 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1703070 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703071 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703072 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703073 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1703074 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703075 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703076 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703077 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703078 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703079 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703080 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703081 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703082 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703083 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703084 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703085 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703086 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1703087 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1703088 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1703089 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1703090 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1703091 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1703092 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1703093 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1703094 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1703095 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703096 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703097 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703098 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1703099 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703100 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703101 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703102 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703103 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703104 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703105 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703106 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703107 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703108 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703109 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703110 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703111 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1703112 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1703113 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1703114 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1703115 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1703116 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1703117 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1703118 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1703119 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1703120 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703121 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703122 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703123 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1703124 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703125 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703126 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703127 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703128 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703129 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703130 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703131 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703132 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703133 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703134 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703135 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703136 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1703137 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1703138 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1703139 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1703140 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1703141 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1703142 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1703143 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1703144 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1703145 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703146 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703147 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703148 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1703149 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703150 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703151 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703152 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703153 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703154 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703155 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703156 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703157 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703158 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703159 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703160 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703161 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1703162 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1703163 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1703164 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1703165 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1703166 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1703167 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1703168 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1703169 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1703170 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703171 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703172 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703173 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1703174 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703175 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703176 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703177 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703178 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703179 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703180 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703181 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703182 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703183 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703184 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703185 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703186 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1703187 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1703188 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1703189 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1703190 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1703191 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1703192 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1703193 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1703194 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1703195 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703196 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703197 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703198 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1703199 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703200 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703201 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703202 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703203 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703204 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703205 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703206 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703207 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703208 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703209 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703210 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703211 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1703212 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1703213 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1703214 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1703215 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1703216 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1703217 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1703218 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1703219 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1703220 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703221 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703222 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703223 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1703224 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703225 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703226 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703227 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703228 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703229 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703230 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703231 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703232 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703233 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703234 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703235 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703236 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1703237 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1703238 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1703239 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1703240 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1703241 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1703242 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1703243 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1703244 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1703245 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703246 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703247 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703248 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1703249 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703250 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703251 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703252 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703253 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703254 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703255 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703256 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703257 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703258 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703259 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703260 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703261 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1703262 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1703263 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1703264 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1703265 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1703266 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1703267 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1703268 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1703269 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1703270 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703271 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703272 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703273 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1703274 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703275 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703276 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703277 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703278 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703279 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703280 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703281 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703282 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703283 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703284 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703285 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703286 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1703287 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1703288 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1703289 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1703290 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1703291 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1703292 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1703293 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1703294 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1703295 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703296 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703297 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703298 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1703299 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703300 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703301 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703302 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703303 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703304 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703305 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703306 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703307 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703308 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703309 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703310 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703311 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1703312 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1703313 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1703314 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1703315 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1703316 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1703317 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1703318 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1703319 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1703320 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703321 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703322 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703323 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1703324 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703325 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703326 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703327 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703328 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703329 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703330 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703331 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703332 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703333 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703334 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703335 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703336 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1703337 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1703338 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1703339 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1703340 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1703341 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1703342 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1703343 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1703344 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1703345 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703346 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703347 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703348 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1703349 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703350 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703351 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703352 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703353 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703354 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703355 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703356 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703357 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703358 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703359 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703360 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703361 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1703362 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1703363 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1703364 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1703365 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1703366 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1703367 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1703368 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1703369 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1703370 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703371 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703372 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703373 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1703374 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703375 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703376 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703377 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703378 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703379 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703380 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703381 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703382 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703383 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703384 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703385 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703386 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1703387 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1703388 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1703389 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1703390 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1703391 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1703392 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1703393 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1703394 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1703395 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703396 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703397 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703398 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1703399 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703400 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703401 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703402 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703403 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703404 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703405 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703406 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703407 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703408 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703409 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703410 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703411 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1703412 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1703413 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1703414 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1703415 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1703416 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1703417 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1703418 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1703419 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1703420 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703421 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703422 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703423 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1703424 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703425 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703426 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703427 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703428 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703429 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703430 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703431 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703432 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703433 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703434 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703435 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703436 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1703437 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1703438 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1703439 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1703440 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1703441 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1703442 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1703443 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1703444 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1703445 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703446 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703447 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703448 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1703449 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703450 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703451 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703452 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703453 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703454 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703455 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703456 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703457 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703458 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703459 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703460 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703461 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1703462 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1703463 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1703464 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1703465 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1703466 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1703467 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1703468 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1703469 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1703470 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703471 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703472 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703473 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1703474 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703475 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703476 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703477 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703478 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703479 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703480 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703481 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703482 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703483 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703484 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703485 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703486 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1703487 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1703488 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1703489 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1703490 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1703491 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1703492 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1703493 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1703494 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1703495 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703496 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703497 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703498 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1703499 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703500 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703501 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703502 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703503 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703504 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703505 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703506 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703507 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703508 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703509 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703510 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703511 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1703512 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1703513 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1703514 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1703515 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1703516 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1703517 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1703518 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1703519 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1703520 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703521 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703522 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703523 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1703524 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703525 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703526 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703527 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703528 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703529 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703530 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703531 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703532 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703533 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703534 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703535 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703536 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1703537 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1703538 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1703539 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1703540 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1703541 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1703542 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1703543 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1703544 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1703545 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703546 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703547 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703548 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1703549 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703550 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703551 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703552 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703553 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703554 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703555 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703556 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703557 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703558 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703559 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703560 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703561 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1703562 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1703563 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1703564 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1703565 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1703566 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1703567 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1703568 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1703569 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1703570 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703571 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703572 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703573 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1703574 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703575 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703576 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703577 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703578 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703579 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703580 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703581 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703582 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703583 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703584 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703585 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703586 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1703587 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1703588 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1703589 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1703590 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1703591 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1703592 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1703593 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1703594 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1703595 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703596 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703597 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703598 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1703599 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703600 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703601 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703602 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703603 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703604 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703605 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703606 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703607 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703608 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703609 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703610 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703611 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1703612 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1703613 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1703614 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1703615 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1703616 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1703617 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1703618 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1703619 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1703620 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703621 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703622 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703623 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1703624 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703625 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703626 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703627 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703628 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703629 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703630 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703631 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703632 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703633 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703634 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703635 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703636 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1703637 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1703638 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1703639 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1703640 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1703641 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1703642 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1703643 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1703644 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1703645 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703646 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703647 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703648 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1703649 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703650 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703651 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703652 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703653 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703654 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703655 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703656 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703657 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703658 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703659 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703660 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703661 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1703662 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1703663 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1703664 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1703665 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1703666 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1703667 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1703668 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1703669 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1703670 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703671 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703672 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703673 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1703674 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703675 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703676 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703677 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703678 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703679 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703680 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703681 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703682 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703683 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703684 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703685 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703686 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1703687 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1703688 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1703689 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1703690 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1703691 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1703692 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1703693 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1703694 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1703695 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703696 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703697 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703698 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1703699 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703700 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703701 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703702 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703703 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703704 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703705 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703706 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703707 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703708 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703709 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703710 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703711 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1703712 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1703713 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1703714 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1703715 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1703716 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1703717 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1703718 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1703719 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1703720 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703721 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703722 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703723 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1703724 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703725 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703726 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703727 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703728 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703729 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703730 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703731 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703732 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703733 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703734 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703735 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703736 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1703737 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1703738 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1703739 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1703740 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1703741 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1703742 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1703743 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1703744 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1703745 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703746 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703747 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703748 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1703749 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703750 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703751 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703752 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703753 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703754 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703755 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703756 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703757 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703758 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703759 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703760 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703761 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1703762 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1703763 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1703764 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1703765 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1703766 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1703767 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1703768 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1703769 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1703770 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703771 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703772 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703773 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1703774 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703775 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703776 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703777 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703778 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703779 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703780 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703781 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703782 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703783 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703784 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703785 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703786 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1703787 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1703788 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1703789 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1703790 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1703791 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1703792 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1703793 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1703794 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1703795 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703796 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703797 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703798 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1703799 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703800 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703801 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703802 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703803 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703804 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703805 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703806 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703807 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703808 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703809 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703810 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703811 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1703812 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1703813 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1703814 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1703815 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1703816 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1703817 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1703818 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1703819 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1703820 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703821 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703822 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703823 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1703824 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703825 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703826 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703827 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703828 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703829 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703830 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703831 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703832 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703833 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703834 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703835 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703836 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1703837 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1703838 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1703839 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1703840 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1703841 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1703842 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1703843 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1703844 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1703845 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703846 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703847 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703848 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1703849 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703850 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703851 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703852 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703853 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703854 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703855 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703856 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703857 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703858 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703859 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703860 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703861 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1703862 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1703863 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1703864 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1703865 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1703866 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1703867 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1703868 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1703869 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1703870 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703871 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703872 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703873 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1703874 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703875 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703876 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703877 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703878 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703879 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703880 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703881 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703882 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703883 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703884 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703885 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703886 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1703887 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1703888 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1703889 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1703890 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1703891 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1703892 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1703893 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1703894 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1703895 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703896 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703897 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703898 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1703899 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703900 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703901 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703902 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703903 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703904 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703905 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703906 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703907 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703908 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703909 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703910 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703911 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1703912 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1703913 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1703914 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1703915 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1703916 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1703917 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1703918 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1703919 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1703920 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703921 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703922 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703923 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1703924 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703925 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703926 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703927 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703928 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703929 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703930 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703931 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703932 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703933 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703934 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703935 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703936 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1703937 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1703938 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1703939 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1703940 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1703941 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1703942 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1703943 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1703944 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1703945 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703946 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703947 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703948 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1703949 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703950 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703951 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703952 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703953 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703954 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703955 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703956 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703957 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703958 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703959 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703960 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703961 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1703962 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1703963 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1703964 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1703965 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1703966 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1703967 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1703968 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1703969 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1703970 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703971 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703972 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703973 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1703974 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703975 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703976 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703977 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703978 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703979 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703980 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703981 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703982 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703983 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703984 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703985 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703986 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1703987 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1703988 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1703989 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1703990 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1703991 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1703992 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1703993 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1703994 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1703995 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703996 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703997 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1703998 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1703999 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704000 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704001 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704002 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704003 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704004 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704005 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704006 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704007 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704008 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704009 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704010 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704011 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1704012 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1704013 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1704014 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1704015 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1704016 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1704017 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1704018 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1704019 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1704020 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704021 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704022 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704023 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1704024 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704025 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704026 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704027 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704028 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704029 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704030 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704031 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704032 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704033 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704034 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704035 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704036 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1704037 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1704038 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1704039 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1704040 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1704041 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1704042 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1704043 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1704044 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1704045 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704046 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704047 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704048 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1704049 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704050 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704051 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704052 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704053 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704054 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704055 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704056 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704057 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704058 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704059 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704060 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704061 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1704062 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1704063 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1704064 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1704065 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1704066 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1704067 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1704068 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1704069 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1704070 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704071 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704072 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704073 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1704074 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704075 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704076 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704077 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704078 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704079 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704080 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704081 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704082 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704083 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704084 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704085 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704086 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1704087 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1704088 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1704089 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1704090 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1704091 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1704092 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1704093 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1704094 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1704095 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704096 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704097 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704098 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1704099 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704100 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704101 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704102 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704103 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704104 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704105 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704106 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704107 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704108 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704109 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704110 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704111 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1704112 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1704113 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1704114 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1704115 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1704116 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1704117 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1704118 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1704119 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1704120 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704121 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704122 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704123 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1704124 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704125 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704126 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704127 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704128 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704129 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704130 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704131 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704132 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704133 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704134 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704135 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704136 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1704137 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1704138 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1704139 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1704140 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1704141 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1704142 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1704143 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1704144 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1704145 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704146 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704147 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704148 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1704149 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704150 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704151 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704152 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704153 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704154 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704155 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704156 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704157 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704158 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704159 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704160 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704161 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1704162 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1704163 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1704164 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1704165 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1704166 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1704167 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1704168 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1704169 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1704170 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704171 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704172 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704173 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1704174 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704175 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704176 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704177 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704178 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704179 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704180 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704181 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704182 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704183 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704184 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704185 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704186 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1704187 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1704188 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1704189 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1704190 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1704191 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1704192 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1704193 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1704194 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1704195 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704196 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704197 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704198 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1704199 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704200 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704201 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704202 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704203 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704204 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704205 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704206 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704207 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704208 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704209 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704210 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704211 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1704212 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1704213 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1704214 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1704215 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1704216 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1704217 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1704218 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1704219 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1704220 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704221 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704222 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704223 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1704224 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704225 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704226 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704227 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704228 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704229 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704230 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704231 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704232 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704233 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704234 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704235 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704236 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1704237 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1704238 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1704239 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1704240 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1704241 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1704242 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1704243 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1704244 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1704245 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704246 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704247 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704248 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1704249 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704250 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704251 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704252 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704253 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704254 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704255 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704256 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704257 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704258 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704259 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704260 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704261 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1704262 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1704263 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1704264 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1704265 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1704266 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1704267 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1704268 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1704269 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1704270 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704271 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704272 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704273 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1704274 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704275 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704276 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704277 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704278 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704279 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704280 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704281 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704282 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704283 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704284 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704285 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704286 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1704287 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1704288 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1704289 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1704290 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1704291 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1704292 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1704293 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1704294 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1704295 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704296 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704297 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704298 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1704299 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704300 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704301 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704302 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704303 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704304 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704305 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704306 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704307 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704308 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704309 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704310 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704311 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1704312 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1704313 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1704314 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1704315 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1704316 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1704317 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1704318 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1704319 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1704320 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704321 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704322 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704323 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1704324 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704325 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704326 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704327 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704328 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704329 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704330 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704331 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704332 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704333 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704334 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704335 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704336 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1704337 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1704338 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1704339 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1704340 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1704341 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1704342 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1704343 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1704344 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1704345 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704346 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704347 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704348 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1704349 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704350 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704351 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704352 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704353 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704354 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704355 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704356 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704357 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704358 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704359 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704360 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704361 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1704362 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1704363 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1704364 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1704365 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1704366 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1704367 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1704368 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1704369 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1704370 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704371 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704372 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704373 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1704374 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704375 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704376 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704377 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704378 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704379 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704380 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704381 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704382 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704383 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704384 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704385 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704386 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1704387 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1704388 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1704389 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1704390 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1704391 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1704392 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1704393 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1704394 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1704395 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704396 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704397 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704398 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1704399 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704400 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704401 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704402 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704403 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704404 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704405 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704406 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704407 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704408 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704409 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704410 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704411 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1704412 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1704413 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1704414 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1704415 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1704416 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1704417 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1704418 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1704419 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1704420 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704421 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704422 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704423 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1704424 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704425 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704426 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704427 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704428 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704429 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704430 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704431 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704432 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704433 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704434 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704435 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704436 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1704437 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1704438 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1704439 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1704440 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1704441 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1704442 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1704443 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1704444 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1704445 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704446 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704447 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704448 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1704449 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704450 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704451 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704452 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704453 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704454 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704455 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704456 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704457 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704458 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704459 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704460 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704461 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1704462 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1704463 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1704464 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1704465 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1704466 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1704467 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1704468 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1704469 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1704470 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704471 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704472 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704473 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1704474 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704475 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704476 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704477 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704478 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704479 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704480 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704481 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704482 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704483 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704484 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704485 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704486 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1704487 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1704488 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1704489 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1704490 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1704491 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1704492 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1704493 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1704494 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1704495 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704496 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704497 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704498 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1704499 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704500 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704501 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704502 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704503 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704504 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704505 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704506 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704507 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704508 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704509 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704510 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704511 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1704512 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1704513 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1704514 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1704515 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1704516 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1704517 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1704518 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1704519 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1704520 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704521 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704522 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704523 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1704524 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704525 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704526 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704527 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704528 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704529 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704530 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704531 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704532 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704533 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704534 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704535 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704536 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1704537 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1704538 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1704539 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1704540 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1704541 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1704542 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1704543 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1704544 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1704545 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704546 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704547 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704548 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1704549 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704550 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704551 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704552 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704553 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704554 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704555 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704556 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704557 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704558 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704559 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704560 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704561 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1704562 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1704563 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1704564 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1704565 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1704566 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1704567 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1704568 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1704569 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1704570 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704571 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704572 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704573 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1704574 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704575 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704576 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704577 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704578 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704579 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704580 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704581 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704582 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704583 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704584 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704585 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704586 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1704587 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1704588 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1704589 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1704590 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1704591 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1704592 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1704593 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1704594 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1704595 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704596 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704597 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704598 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1704599 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704600 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704601 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704602 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704603 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704604 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704605 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704606 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704607 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704608 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704609 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704610 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704611 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1704612 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1704613 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1704614 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1704615 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1704616 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1704617 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1704618 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1704619 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1704620 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704621 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704622 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704623 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1704624 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704625 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704626 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704627 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704628 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704629 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704630 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704631 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704632 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704633 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704634 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704635 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704636 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1704637 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1704638 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1704639 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1704640 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1704641 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1704642 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1704643 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1704644 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1704645 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704646 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704647 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704648 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1704649 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704650 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704651 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704652 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704653 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704654 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704655 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704656 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704657 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704658 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704659 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704660 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704661 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1704662 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1704663 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1704664 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1704665 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1704666 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1704667 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1704668 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1704669 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1704670 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704671 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704672 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704673 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1704674 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704675 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704676 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704677 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704678 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704679 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704680 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704681 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704682 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704683 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704684 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704685 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704686 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1704687 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1704688 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1704689 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1704690 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1704691 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1704692 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1704693 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1704694 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1704695 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704696 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704697 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704698 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1704699 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704700 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704701 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704702 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704703 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704704 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704705 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704706 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704707 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704708 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704709 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704710 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704711 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1704712 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1704713 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1704714 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1704715 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1704716 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1704717 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1704718 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1704719 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1704720 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704721 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704722 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704723 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1704724 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704725 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704726 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704727 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704728 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704729 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704730 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704731 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704732 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704733 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704734 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704735 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704736 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1704737 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1704738 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1704739 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1704740 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1704741 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1704742 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1704743 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1704744 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1704745 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704746 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704747 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704748 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1704749 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704750 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704751 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704752 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704753 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704754 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704755 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704756 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704757 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704758 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704759 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704760 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704761 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1704762 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1704763 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1704764 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1704765 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1704766 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1704767 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1704768 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1704769 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1704770 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704771 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704772 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704773 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1704774 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704775 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704776 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704777 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704778 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704779 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704780 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704781 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704782 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704783 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704784 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704785 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704786 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1704787 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1704788 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1704789 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1704790 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1704791 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1704792 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1704793 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1704794 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1704795 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704796 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704797 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704798 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1704799 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704800 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704801 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704802 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704803 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704804 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704805 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704806 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704807 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704808 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704809 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704810 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704811 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1704812 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1704813 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1704814 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1704815 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1704816 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1704817 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1704818 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1704819 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1704820 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704821 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704822 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704823 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1704824 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704825 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704826 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704827 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704828 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704829 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704830 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704831 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704832 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704833 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704834 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704835 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704836 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1704837 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1704838 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1704839 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1704840 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1704841 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1704842 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1704843 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1704844 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1704845 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704846 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704847 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704848 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1704849 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704850 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704851 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704852 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704853 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704854 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704855 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704856 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704857 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704858 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704859 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704860 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704861 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1704862 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1704863 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1704864 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1704865 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1704866 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1704867 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1704868 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1704869 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1704870 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704871 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704872 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704873 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1704874 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704875 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704876 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704877 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704878 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704879 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704880 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704881 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704882 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704883 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704884 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704885 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704886 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1704887 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1704888 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1704889 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1704890 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1704891 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1704892 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1704893 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1704894 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1704895 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704896 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704897 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704898 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1704899 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704900 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704901 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704902 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704903 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704904 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704905 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704906 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704907 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704908 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704909 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704910 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704911 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1704912 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1704913 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1704914 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1704915 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1704916 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1704917 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1704918 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1704919 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1704920 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704921 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704922 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704923 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1704924 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704925 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704926 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704927 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704928 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704929 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704930 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704931 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704932 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704933 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704934 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704935 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704936 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1704937 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1704938 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1704939 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1704940 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1704941 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1704942 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1704943 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1704944 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1704945 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704946 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704947 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704948 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1704949 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704950 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704951 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704952 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704953 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704954 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704955 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704956 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704957 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704958 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704959 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704960 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704961 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1704962 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1704963 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1704964 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1704965 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1704966 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1704967 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1704968 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1704969 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1704970 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704971 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704972 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704973 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1704974 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704975 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704976 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704977 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704978 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704979 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704980 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704981 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704982 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704983 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704984 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704985 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704986 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1704987 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1704988 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1704989 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1704990 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1704991 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1704992 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1704993 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1704994 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1704995 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704996 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704997 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1704998 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1704999 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705000 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705001 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705002 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705003 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705004 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705005 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705006 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705007 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705008 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705009 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705010 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705011 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1705012 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1705013 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1705014 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1705015 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1705016 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1705017 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1705018 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1705019 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1705020 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705021 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705022 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705023 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1705024 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705025 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705026 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705027 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705028 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705029 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705030 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705031 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705032 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705033 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705034 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705035 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705036 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1705037 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1705038 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1705039 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1705040 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1705041 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1705042 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1705043 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1705044 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1705045 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705046 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705047 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705048 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1705049 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705050 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705051 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705052 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705053 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705054 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705055 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705056 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705057 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705058 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705059 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705060 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705061 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1705062 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1705063 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1705064 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1705065 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1705066 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1705067 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1705068 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1705069 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1705070 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705071 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705072 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705073 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1705074 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705075 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705076 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705077 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705078 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705079 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705080 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705081 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705082 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705083 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705084 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705085 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705086 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1705087 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1705088 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1705089 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1705090 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1705091 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1705092 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1705093 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1705094 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1705095 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705096 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705097 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705098 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1705099 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705100 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705101 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705102 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705103 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705104 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705105 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705106 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705107 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705108 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705109 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705110 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705111 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1705112 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1705113 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1705114 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1705115 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1705116 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1705117 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1705118 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1705119 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1705120 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705121 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705122 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705123 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1705124 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705125 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705126 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705127 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705128 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705129 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705130 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705131 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705132 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705133 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705134 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705135 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705136 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1705137 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1705138 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1705139 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1705140 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1705141 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1705142 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1705143 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1705144 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1705145 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705146 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705147 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705148 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1705149 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705150 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705151 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705152 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705153 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705154 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705155 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705156 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705157 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705158 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705159 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705160 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705161 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1705162 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1705163 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1705164 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1705165 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1705166 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1705167 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1705168 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1705169 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1705170 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705171 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705172 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705173 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1705174 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705175 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705176 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705177 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705178 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705179 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705180 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705181 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705182 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705183 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705184 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705185 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705186 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1705187 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1705188 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1705189 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1705190 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1705191 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1705192 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1705193 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1705194 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1705195 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705196 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705197 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705198 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1705199 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705200 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705201 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705202 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705203 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705204 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705205 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705206 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705207 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705208 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705209 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705210 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705211 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1705212 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1705213 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1705214 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1705215 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1705216 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1705217 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1705218 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1705219 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1705220 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705221 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705222 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705223 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1705224 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705225 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705226 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705227 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705228 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705229 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705230 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705231 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705232 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705233 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705234 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705235 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705236 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1705237 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1705238 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1705239 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1705240 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1705241 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1705242 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1705243 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1705244 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1705245 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705246 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705247 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705248 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1705249 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705250 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705251 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705252 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705253 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705254 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705255 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705256 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705257 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705258 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705259 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705260 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705261 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1705262 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1705263 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1705264 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1705265 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1705266 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1705267 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1705268 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1705269 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1705270 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705271 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705272 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705273 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1705274 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705275 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705276 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705277 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705278 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705279 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705280 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705281 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705282 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705283 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705284 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705285 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705286 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1705287 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1705288 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1705289 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1705290 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1705291 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1705292 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1705293 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1705294 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1705295 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705296 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705297 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705298 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1705299 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705300 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705301 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705302 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705303 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705304 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705305 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705306 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705307 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705308 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705309 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705310 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705311 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1705312 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1705313 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1705314 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1705315 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1705316 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1705317 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1705318 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1705319 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1705320 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705321 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705322 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705323 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1705324 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705325 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705326 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705327 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705328 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705329 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705330 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705331 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705332 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705333 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705334 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705335 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705336 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1705337 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1705338 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1705339 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1705340 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1705341 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1705342 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1705343 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1705344 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1705345 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705346 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705347 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705348 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1705349 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705350 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705351 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705352 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705353 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705354 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705355 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705356 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705357 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705358 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705359 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705360 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705361 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1705362 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1705363 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1705364 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1705365 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1705366 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1705367 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1705368 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1705369 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1705370 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705371 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705372 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705373 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1705374 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705375 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705376 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705377 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705378 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705379 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705380 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705381 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705382 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705383 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705384 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705385 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705386 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1705387 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1705388 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1705389 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1705390 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1705391 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1705392 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1705393 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1705394 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1705395 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705396 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705397 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705398 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1705399 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705400 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705401 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705402 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705403 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705404 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705405 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705406 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705407 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705408 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705409 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705410 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705411 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1705412 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1705413 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1705414 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1705415 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1705416 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1705417 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1705418 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1705419 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1705420 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705421 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705422 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705423 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1705424 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705425 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705426 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705427 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705428 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705429 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705430 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705431 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705432 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705433 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705434 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705435 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705436 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1705437 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1705438 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1705439 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1705440 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1705441 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1705442 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1705443 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1705444 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1705445 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705446 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705447 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705448 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1705449 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705450 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705451 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705452 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705453 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705454 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705455 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705456 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705457 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705458 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705459 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705460 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705461 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1705462 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1705463 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1705464 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1705465 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1705466 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1705467 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1705468 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1705469 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1705470 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705471 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705472 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705473 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1705474 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705475 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705476 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705477 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705478 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705479 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705480 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705481 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705482 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705483 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705484 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705485 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705486 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1705487 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1705488 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1705489 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1705490 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1705491 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1705492 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1705493 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1705494 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1705495 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705496 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705497 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705498 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1705499 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705500 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705501 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705502 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705503 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705504 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705505 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705506 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705507 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705508 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705509 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705510 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705511 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1705512 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1705513 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1705514 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1705515 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1705516 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1705517 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1705518 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1705519 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1705520 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705521 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705522 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705523 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1705524 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705525 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705526 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705527 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705528 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705529 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705530 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705531 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705532 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705533 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705534 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705535 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705536 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1705537 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1705538 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1705539 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1705540 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1705541 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1705542 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1705543 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1705544 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1705545 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705546 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705547 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705548 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1705549 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705550 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705551 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705552 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705553 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705554 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705555 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705556 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705557 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705558 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705559 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705560 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705561 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1705562 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1705563 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1705564 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1705565 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1705566 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1705567 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1705568 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1705569 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1705570 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705571 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705572 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705573 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1705574 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705575 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705576 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705577 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705578 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705579 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705580 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705581 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705582 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705583 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705584 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705585 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705586 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1705587 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1705588 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1705589 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1705590 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1705591 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1705592 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1705593 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1705594 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1705595 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705596 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705597 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705598 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1705599 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705600 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705601 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705602 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705603 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705604 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705605 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705606 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705607 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705608 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705609 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705610 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705611 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1705612 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1705613 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1705614 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1705615 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1705616 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1705617 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1705618 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1705619 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1705620 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705621 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705622 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705623 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1705624 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705625 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705626 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705627 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705628 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705629 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705630 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705631 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705632 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705633 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705634 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705635 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705636 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1705637 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1705638 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1705639 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1705640 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1705641 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1705642 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1705643 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1705644 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1705645 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705646 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705647 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705648 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1705649 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705650 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705651 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705652 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705653 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705654 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705655 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705656 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705657 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705658 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705659 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705660 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705661 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1705662 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1705663 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1705664 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1705665 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1705666 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1705667 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1705668 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1705669 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1705670 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705671 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705672 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705673 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1705674 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705675 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705676 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705677 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705678 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705679 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705680 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705681 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705682 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705683 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705684 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705685 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705686 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1705687 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1705688 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1705689 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1705690 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1705691 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1705692 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1705693 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1705694 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1705695 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705696 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705697 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705698 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1705699 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705700 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705701 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705702 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705703 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705704 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705705 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705706 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705707 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705708 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705709 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705710 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705711 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1705712 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1705713 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1705714 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1705715 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1705716 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1705717 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1705718 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1705719 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1705720 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705721 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705722 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705723 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1705724 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705725 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705726 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705727 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705728 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705729 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705730 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705731 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705732 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705733 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705734 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705735 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705736 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1705737 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1705738 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1705739 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1705740 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1705741 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1705742 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1705743 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1705744 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1705745 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705746 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705747 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705748 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1705749 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705750 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705751 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705752 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705753 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705754 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705755 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705756 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705757 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705758 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705759 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705760 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705761 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1705762 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1705763 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1705764 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1705765 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1705766 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1705767 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1705768 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1705769 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1705770 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705771 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705772 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705773 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1705774 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705775 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705776 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705777 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705778 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705779 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705780 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705781 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705782 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705783 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705784 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705785 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705786 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1705787 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1705788 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1705789 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1705790 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1705791 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1705792 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1705793 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1705794 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1705795 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705796 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705797 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705798 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1705799 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705800 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705801 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705802 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705803 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705804 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705805 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705806 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705807 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705808 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705809 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705810 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705811 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1705812 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1705813 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1705814 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1705815 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1705816 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1705817 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1705818 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1705819 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1705820 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705821 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705822 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705823 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1705824 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705825 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705826 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705827 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705828 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705829 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705830 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705831 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705832 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705833 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705834 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705835 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705836 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1705837 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1705838 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1705839 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1705840 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1705841 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1705842 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1705843 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1705844 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1705845 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705846 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705847 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705848 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1705849 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705850 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705851 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705852 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705853 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705854 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705855 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705856 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705857 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705858 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705859 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705860 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705861 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1705862 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1705863 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1705864 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1705865 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1705866 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1705867 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1705868 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1705869 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1705870 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705871 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705872 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705873 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1705874 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705875 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705876 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705877 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705878 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705879 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705880 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705881 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705882 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705883 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705884 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705885 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705886 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1705887 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1705888 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1705889 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1705890 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1705891 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1705892 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1705893 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1705894 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1705895 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705896 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705897 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705898 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1705899 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705900 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705901 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705902 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705903 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705904 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705905 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705906 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705907 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705908 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705909 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705910 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705911 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1705912 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1705913 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1705914 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1705915 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1705916 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1705917 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1705918 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1705919 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1705920 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705921 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705922 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705923 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1705924 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705925 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705926 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705927 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705928 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705929 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705930 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705931 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705932 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705933 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705934 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705935 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705936 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1705937 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1705938 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1705939 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1705940 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1705941 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1705942 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1705943 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1705944 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1705945 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705946 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705947 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705948 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1705949 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705950 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705951 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705952 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705953 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705954 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705955 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705956 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705957 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705958 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705959 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705960 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705961 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1705962 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1705963 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1705964 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1705965 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1705966 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1705967 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1705968 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1705969 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1705970 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705971 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705972 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705973 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1705974 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705975 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705976 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705977 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705978 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705979 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705980 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705981 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705982 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705983 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705984 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705985 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705986 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1705987 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1705988 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1705989 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1705990 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1705991 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1705992 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1705993 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1705994 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1705995 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705996 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705997 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1705998 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1705999 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706000 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706001 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706002 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706003 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706004 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706005 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706006 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706007 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706008 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706009 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706010 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706011 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1706012 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1706013 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1706014 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1706015 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1706016 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1706017 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1706018 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1706019 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1706020 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706021 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706022 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706023 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1706024 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706025 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706026 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706027 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706028 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706029 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706030 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706031 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706032 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706033 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706034 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706035 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706036 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1706037 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1706038 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1706039 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1706040 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1706041 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1706042 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1706043 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1706044 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1706045 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706046 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706047 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706048 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1706049 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706050 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706051 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706052 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706053 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706054 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706055 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706056 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706057 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706058 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706059 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706060 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706061 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1706062 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1706063 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1706064 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1706065 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1706066 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1706067 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1706068 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1706069 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1706070 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706071 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706072 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706073 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1706074 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706075 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706076 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706077 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706078 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706079 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706080 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706081 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706082 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706083 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706084 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706085 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706086 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1706087 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1706088 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1706089 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1706090 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1706091 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1706092 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1706093 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1706094 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1706095 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706096 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706097 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706098 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1706099 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706100 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706101 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706102 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706103 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706104 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706105 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706106 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706107 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706108 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706109 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706110 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706111 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1706112 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1706113 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1706114 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1706115 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1706116 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1706117 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1706118 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1706119 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1706120 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706121 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706122 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706123 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1706124 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706125 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706126 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706127 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706128 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706129 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706130 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706131 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706132 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706133 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706134 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706135 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706136 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1706137 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1706138 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1706139 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1706140 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1706141 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1706142 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1706143 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1706144 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1706145 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706146 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706147 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706148 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1706149 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706150 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706151 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706152 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706153 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706154 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706155 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706156 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706157 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706158 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706159 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706160 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706161 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1706162 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1706163 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1706164 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1706165 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1706166 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1706167 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1706168 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1706169 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1706170 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706171 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706172 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706173 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1706174 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706175 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706176 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706177 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706178 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706179 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706180 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706181 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706182 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706183 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706184 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706185 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706186 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1706187 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1706188 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1706189 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1706190 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1706191 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1706192 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1706193 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1706194 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1706195 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706196 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706197 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706198 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1706199 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706200 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706201 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706202 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706203 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706204 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706205 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706206 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706207 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706208 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706209 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706210 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706211 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1706212 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1706213 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1706214 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1706215 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1706216 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1706217 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1706218 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1706219 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1706220 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706221 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706222 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706223 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1706224 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706225 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706226 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706227 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706228 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706229 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706230 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706231 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706232 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706233 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706234 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706235 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706236 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1706237 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1706238 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1706239 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1706240 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1706241 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1706242 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1706243 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1706244 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1706245 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706246 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706247 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706248 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1706249 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706250 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706251 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706252 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706253 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706254 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706255 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706256 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706257 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706258 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706259 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706260 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706261 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1706262 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1706263 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1706264 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1706265 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1706266 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1706267 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1706268 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1706269 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1706270 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706271 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706272 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706273 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1706274 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706275 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706276 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706277 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706278 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706279 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706280 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706281 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706282 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706283 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706284 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706285 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706286 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1706287 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1706288 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1706289 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1706290 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1706291 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1706292 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1706293 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1706294 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1706295 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706296 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706297 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706298 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1706299 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706300 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706301 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706302 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706303 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706304 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706305 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706306 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706307 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706308 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706309 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706310 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706311 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1706312 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1706313 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1706314 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1706315 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1706316 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1706317 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1706318 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1706319 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1706320 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706321 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706322 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706323 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1706324 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706325 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706326 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706327 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706328 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706329 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706330 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706331 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706332 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706333 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706334 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706335 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706336 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1706337 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1706338 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1706339 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1706340 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1706341 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1706342 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1706343 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1706344 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1706345 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706346 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706347 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706348 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1706349 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706350 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706351 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706352 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706353 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706354 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706355 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706356 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706357 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706358 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706359 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706360 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706361 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1706362 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1706363 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1706364 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1706365 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1706366 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1706367 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1706368 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1706369 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1706370 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706371 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706372 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706373 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1706374 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706375 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706376 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706377 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706378 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706379 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706380 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706381 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706382 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706383 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706384 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706385 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706386 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1706387 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1706388 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1706389 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1706390 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1706391 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1706392 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1706393 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1706394 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1706395 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706396 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706397 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706398 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1706399 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706400 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706401 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706402 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706403 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706404 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706405 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706406 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706407 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706408 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706409 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706410 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706411 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1706412 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1706413 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1706414 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1706415 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1706416 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1706417 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1706418 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1706419 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1706420 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706421 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706422 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706423 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1706424 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706425 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706426 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706427 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706428 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706429 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706430 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706431 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706432 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706433 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706434 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706435 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706436 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1706437 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1706438 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1706439 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1706440 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1706441 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1706442 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1706443 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1706444 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1706445 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706446 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706447 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706448 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1706449 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706450 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706451 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706452 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706453 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706454 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706455 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706456 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706457 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706458 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706459 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706460 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706461 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1706462 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1706463 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1706464 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1706465 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1706466 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1706467 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1706468 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1706469 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1706470 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706471 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706472 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706473 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1706474 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706475 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706476 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706477 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706478 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706479 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706480 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706481 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706482 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706483 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706484 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706485 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706486 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1706487 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1706488 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1706489 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1706490 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1706491 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1706492 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1706493 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1706494 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1706495 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706496 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706497 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706498 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1706499 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706500 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706501 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706502 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706503 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706504 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706505 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706506 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706507 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706508 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706509 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706510 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706511 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1706512 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1706513 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1706514 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1706515 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1706516 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1706517 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1706518 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1706519 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1706520 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706521 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706522 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706523 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1706524 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706525 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706526 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706527 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706528 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706529 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706530 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706531 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706532 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706533 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706534 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706535 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706536 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1706537 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1706538 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1706539 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1706540 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1706541 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1706542 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1706543 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1706544 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1706545 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706546 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706547 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706548 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1706549 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706550 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706551 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706552 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706553 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706554 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706555 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706556 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706557 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706558 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706559 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706560 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706561 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1706562 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1706563 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1706564 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1706565 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1706566 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1706567 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1706568 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1706569 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1706570 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706571 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706572 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706573 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1706574 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706575 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706576 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706577 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706578 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706579 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706580 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706581 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706582 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706583 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706584 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706585 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706586 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1706587 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1706588 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1706589 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1706590 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1706591 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1706592 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1706593 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1706594 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1706595 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706596 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706597 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706598 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1706599 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706600 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706601 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706602 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706603 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706604 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706605 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706606 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706607 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706608 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706609 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706610 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706611 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1706612 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1706613 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1706614 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1706615 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1706616 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1706617 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1706618 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1706619 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1706620 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706621 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706622 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706623 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1706624 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706625 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706626 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706627 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706628 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706629 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706630 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706631 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706632 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706633 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706634 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706635 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706636 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1706637 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1706638 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1706639 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1706640 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1706641 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1706642 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1706643 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1706644 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1706645 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706646 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706647 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706648 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1706649 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706650 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706651 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706652 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706653 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706654 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706655 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706656 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706657 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706658 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706659 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706660 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706661 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1706662 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1706663 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1706664 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1706665 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1706666 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1706667 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1706668 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1706669 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1706670 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706671 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706672 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706673 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1706674 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706675 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706676 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706677 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706678 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706679 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706680 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706681 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706682 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706683 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706684 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706685 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706686 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1706687 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1706688 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1706689 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1706690 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1706691 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1706692 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1706693 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1706694 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1706695 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706696 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706697 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706698 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1706699 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706700 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706701 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706702 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706703 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706704 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706705 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706706 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706707 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706708 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706709 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706710 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706711 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1706712 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1706713 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1706714 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1706715 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1706716 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1706717 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1706718 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1706719 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1706720 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706721 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706722 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706723 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1706724 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706725 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706726 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706727 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706728 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706729 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706730 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706731 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706732 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706733 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706734 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706735 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706736 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1706737 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1706738 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1706739 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1706740 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1706741 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1706742 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1706743 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1706744 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1706745 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706746 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706747 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706748 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1706749 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706750 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706751 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706752 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706753 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706754 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706755 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706756 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706757 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706758 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706759 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706760 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706761 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1706762 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1706763 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1706764 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1706765 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1706766 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1706767 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1706768 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1706769 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1706770 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706771 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706772 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706773 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1706774 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706775 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706776 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706777 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706778 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706779 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706780 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706781 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706782 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706783 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706784 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706785 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706786 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1706787 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1706788 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1706789 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1706790 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1706791 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1706792 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1706793 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1706794 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1706795 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706796 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706797 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706798 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1706799 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706800 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706801 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706802 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706803 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706804 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706805 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706806 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706807 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706808 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706809 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706810 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706811 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1706812 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1706813 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1706814 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1706815 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1706816 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1706817 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1706818 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1706819 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1706820 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706821 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706822 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706823 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1706824 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706825 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706826 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706827 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706828 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706829 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706830 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706831 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706832 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706833 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706834 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706835 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706836 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1706837 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1706838 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1706839 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1706840 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1706841 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1706842 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1706843 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1706844 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1706845 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706846 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706847 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706848 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1706849 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706850 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706851 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706852 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706853 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706854 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706855 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706856 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706857 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706858 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706859 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706860 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706861 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1706862 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1706863 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1706864 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1706865 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1706866 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1706867 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1706868 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1706869 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1706870 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706871 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706872 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706873 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1706874 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706875 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706876 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706877 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706878 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706879 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706880 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706881 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706882 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706883 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706884 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706885 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706886 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1706887 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1706888 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1706889 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1706890 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1706891 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1706892 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1706893 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1706894 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1706895 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706896 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706897 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706898 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1706899 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706900 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706901 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706902 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706903 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706904 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706905 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706906 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706907 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706908 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706909 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706910 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706911 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1706912 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1706913 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1706914 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1706915 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1706916 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1706917 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1706918 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1706919 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1706920 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706921 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706922 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706923 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1706924 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706925 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706926 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706927 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706928 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706929 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706930 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706931 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706932 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706933 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706934 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706935 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706936 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1706937 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1706938 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1706939 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1706940 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1706941 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1706942 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1706943 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0x1
****************** cycle 1706944 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1706945 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706946 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706947 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706948 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1706949 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706950 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706951 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706952 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706953 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706954 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706955 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706956 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706957 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706958 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706959 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706960 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706961 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1706962 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1706963 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1706964 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1706965 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1706966 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1706967 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1706968 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0x1
****************** cycle 1706969 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1706970 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706971 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706972 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706973 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1706974 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706975 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706976 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706977 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706978 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706979 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706980 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706981 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706982 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706983 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706984 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706985 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706986 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1706987 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1706988 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1706989 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1706990 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1706991 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1706992 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1706993 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0x1
****************** cycle 1706994 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1706995 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706996 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706997 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1706998 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1706999 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707000 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707001 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707002 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707003 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707004 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707005 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707006 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707007 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707008 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707009 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707010 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707011 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1707012 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1707013 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1707014 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1707015 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1707016 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1707017 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1707018 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1707019 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1707020 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707021 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707022 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707023 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1707024 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707025 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707026 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707027 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707028 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707029 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707030 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707031 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707032 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707033 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707034 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707035 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707036 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1707037 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1707038 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1707039 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1707040 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1707041 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1707042 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1707043 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1707044 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1707045 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707046 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707047 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707048 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1707049 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707050 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707051 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707052 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707053 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707054 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707055 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707056 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707057 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707058 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707059 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707060 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707061 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1707062 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1707063 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1707064 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1707065 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1707066 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1707067 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1707068 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1707069 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1707070 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707071 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707072 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707073 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1707074 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707075 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707076 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707077 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707078 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707079 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707080 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707081 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707082 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707083 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707084 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707085 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707086 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1707087 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1707088 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1707089 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1707090 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1707091 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1707092 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1707093 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1707094 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1707095 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707096 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707097 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707098 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1707099 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707100 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707101 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707102 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707103 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707104 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707105 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707106 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707107 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707108 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707109 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707110 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707111 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1707112 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1707113 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1707114 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1707115 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1707116 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1707117 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1707118 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1707119 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1707120 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707121 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707122 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707123 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1707124 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707125 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707126 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707127 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707128 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707129 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707130 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707131 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707132 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707133 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707134 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707135 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707136 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1707137 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1707138 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1707139 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1707140 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1707141 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1707142 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1707143 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1707144 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1707145 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707146 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707147 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707148 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1707149 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707150 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707151 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707152 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707153 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707154 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707155 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707156 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707157 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707158 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707159 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707160 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707161 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1707162 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1707163 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1707164 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1707165 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1707166 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1707167 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1707168 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1707169 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1707170 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707171 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707172 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707173 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1707174 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707175 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707176 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707177 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707178 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707179 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707180 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707181 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707182 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707183 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707184 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707185 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707186 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1707187 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1707188 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1707189 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1707190 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1707191 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1707192 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1707193 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1707194 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1707195 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707196 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707197 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707198 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1707199 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707200 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707201 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707202 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707203 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707204 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707205 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707206 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707207 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707208 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707209 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707210 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707211 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1707212 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1707213 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1707214 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1707215 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1707216 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1707217 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1707218 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1707219 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1707220 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707221 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707222 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707223 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1707224 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707225 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707226 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707227 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707228 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707229 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707230 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707231 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707232 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707233 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707234 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707235 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707236 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1707237 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1707238 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1707239 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1707240 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1707241 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1707242 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1707243 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1707244 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1707245 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707246 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707247 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707248 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1707249 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707250 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707251 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707252 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707253 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707254 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707255 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707256 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707257 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707258 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707259 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707260 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707261 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1707262 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1707263 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1707264 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1707265 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1707266 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1707267 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1707268 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1707269 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1707270 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707271 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707272 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707273 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1707274 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707275 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707276 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707277 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707278 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707279 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707280 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707281 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707282 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707283 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707284 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707285 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707286 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1707287 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1707288 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1707289 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1707290 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1707291 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1707292 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1707293 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1707294 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1707295 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707296 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707297 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707298 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1707299 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707300 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707301 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707302 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707303 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707304 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707305 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707306 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707307 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707308 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707309 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707310 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707311 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1707312 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1707313 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1707314 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1707315 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1707316 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1707317 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1707318 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1707319 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1707320 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707321 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707322 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707323 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1707324 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707325 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707326 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707327 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707328 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707329 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707330 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707331 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707332 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707333 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707334 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707335 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707336 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1707337 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1707338 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1707339 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1707340 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1707341 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1707342 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1707343 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1707344 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1707345 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707346 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707347 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707348 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1707349 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707350 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707351 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707352 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707353 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707354 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707355 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707356 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707357 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707358 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707359 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707360 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707361 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1707362 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1707363 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1707364 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1707365 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1707366 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1707367 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1707368 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1707369 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1707370 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707371 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707372 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707373 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1707374 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707375 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707376 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707377 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707378 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707379 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707380 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707381 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707382 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707383 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707384 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707385 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707386 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1707387 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1707388 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1707389 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1707390 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1707391 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1707392 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1707393 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1707394 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1707395 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707396 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707397 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707398 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1707399 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707400 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707401 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707402 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707403 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707404 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707405 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707406 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707407 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707408 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707409 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707410 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707411 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1707412 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1707413 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1707414 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1707415 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1707416 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1707417 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1707418 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1707419 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1707420 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707421 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707422 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707423 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1707424 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707425 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707426 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707427 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707428 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707429 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707430 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707431 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707432 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707433 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707434 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707435 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707436 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1707437 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1707438 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1707439 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1707440 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1707441 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1707442 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1707443 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1707444 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1707445 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707446 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707447 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707448 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1707449 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707450 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707451 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707452 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707453 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707454 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707455 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707456 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707457 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707458 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707459 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707460 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707461 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1707462 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1707463 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1707464 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1707465 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1707466 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1707467 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1707468 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1707469 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1707470 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707471 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707472 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707473 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1707474 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707475 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707476 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707477 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707478 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707479 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707480 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707481 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707482 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707483 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707484 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707485 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707486 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1707487 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1707488 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1707489 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1707490 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1707491 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1707492 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1707493 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1707494 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1707495 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707496 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707497 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707498 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1707499 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707500 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707501 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707502 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707503 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707504 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707505 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707506 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707507 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707508 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707509 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707510 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707511 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1707512 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1707513 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1707514 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1707515 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1707516 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1707517 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1707518 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1707519 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1707520 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707521 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707522 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707523 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1707524 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707525 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707526 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707527 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707528 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707529 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707530 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707531 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707532 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707533 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707534 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707535 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707536 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1707537 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1707538 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1707539 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1707540 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1707541 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1707542 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1707543 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1707544 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1707545 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707546 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707547 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707548 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1707549 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707550 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707551 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707552 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707553 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707554 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707555 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707556 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707557 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707558 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707559 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707560 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707561 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1707562 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1707563 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1707564 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1707565 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1707566 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1707567 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1707568 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1707569 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1707570 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707571 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707572 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707573 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1707574 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707575 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707576 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707577 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707578 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707579 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707580 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707581 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707582 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707583 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707584 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707585 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707586 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1707587 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1707588 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1707589 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1707590 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1707591 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1707592 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1707593 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1707594 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1707595 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707596 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707597 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707598 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1707599 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707600 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707601 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707602 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707603 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707604 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707605 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707606 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707607 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707608 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707609 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707610 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707611 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1707612 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1707613 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1707614 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1707615 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1707616 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1707617 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1707618 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1707619 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1707620 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707621 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707622 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707623 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1707624 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707625 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707626 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707627 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707628 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707629 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707630 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707631 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707632 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707633 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707634 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707635 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707636 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1707637 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1707638 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1707639 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1707640 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1707641 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1707642 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1707643 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1707644 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1707645 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707646 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707647 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707648 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1707649 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707650 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707651 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707652 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707653 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707654 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707655 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707656 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707657 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707658 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707659 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707660 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707661 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1707662 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1707663 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1707664 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1707665 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1707666 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1707667 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1707668 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1707669 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1707670 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707671 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707672 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707673 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1707674 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707675 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707676 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707677 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707678 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707679 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707680 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707681 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707682 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707683 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707684 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707685 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707686 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1707687 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1707688 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1707689 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1707690 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1707691 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1707692 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1707693 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1707694 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1707695 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707696 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707697 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707698 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1707699 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707700 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707701 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707702 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707703 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707704 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707705 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707706 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707707 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707708 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707709 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707710 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707711 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1707712 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1707713 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1707714 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1707715 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1707716 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1707717 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1707718 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0x1
****************** cycle 1707719 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1707720 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707721 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707722 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707723 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1707724 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707725 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707726 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707727 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707728 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707729 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707730 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707731 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707732 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707733 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707734 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707735 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707736 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1707737 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1707738 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1707739 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1707740 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1707741 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1707742 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1707743 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1707744 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1707745 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707746 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707747 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707748 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1707749 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707750 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707751 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707752 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707753 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707754 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707755 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707756 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707757 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707758 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707759 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707760 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707761 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1707762 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1707763 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1707764 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1707765 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1707766 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1707767 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1707768 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1707769 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1707770 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707771 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707772 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707773 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1707774 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707775 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707776 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707777 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707778 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707779 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707780 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707781 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707782 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707783 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707784 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707785 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707786 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1707787 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1707788 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1707789 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1707790 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1707791 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1707792 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1707793 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1707794 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1707795 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707796 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707797 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707798 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1707799 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707800 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707801 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707802 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707803 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707804 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707805 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707806 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707807 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707808 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707809 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707810 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707811 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1707812 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1707813 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1707814 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1707815 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1707816 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1707817 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1707818 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1707819 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1707820 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707821 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707822 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707823 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1707824 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707825 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707826 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707827 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707828 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707829 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707830 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707831 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707832 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707833 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707834 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707835 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707836 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1707837 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1707838 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1707839 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1707840 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1707841 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1707842 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1707843 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1707844 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1707845 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707846 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707847 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707848 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1707849 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707850 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707851 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707852 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707853 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707854 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707855 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707856 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707857 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707858 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707859 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707860 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707861 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1707862 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1707863 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1707864 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1707865 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1707866 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1707867 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1707868 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1707869 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1707870 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707871 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707872 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707873 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1707874 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707875 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707876 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707877 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707878 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707879 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707880 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707881 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707882 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707883 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707884 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707885 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707886 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1707887 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1707888 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1707889 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1707890 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1707891 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1707892 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1707893 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1707894 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1707895 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707896 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707897 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707898 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1707899 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707900 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707901 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707902 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707903 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707904 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707905 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707906 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707907 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707908 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707909 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707910 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707911 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1707912 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1707913 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1707914 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1707915 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1707916 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1707917 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1707918 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1707919 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1707920 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707921 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707922 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707923 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1707924 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707925 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707926 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707927 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707928 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707929 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707930 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707931 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707932 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707933 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707934 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707935 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707936 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1707937 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1707938 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1707939 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1707940 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1707941 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1707942 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1707943 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1707944 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1707945 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707946 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707947 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707948 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1707949 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707950 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707951 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707952 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707953 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707954 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707955 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707956 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707957 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707958 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707959 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707960 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707961 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1707962 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1707963 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1707964 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1707965 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1707966 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1707967 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1707968 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1707969 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1707970 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707971 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707972 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707973 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1707974 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707975 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707976 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707977 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707978 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707979 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707980 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707981 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707982 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707983 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707984 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707985 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707986 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1707987 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1707988 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1707989 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1707990 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1707991 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1707992 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1707993 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1707994 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1707995 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707996 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707997 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1707998 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1707999 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708000 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708001 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708002 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708003 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708004 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708005 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708006 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708007 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708008 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708009 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708010 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708011 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1708012 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1708013 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1708014 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1708015 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1708016 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1708017 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1708018 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1708019 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1708020 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708021 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708022 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708023 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1708024 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708025 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708026 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708027 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708028 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708029 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708030 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708031 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708032 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708033 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708034 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708035 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708036 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1708037 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1708038 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1708039 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1708040 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1708041 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1708042 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1708043 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1708044 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1708045 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708046 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708047 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708048 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1708049 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708050 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708051 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708052 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708053 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708054 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708055 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708056 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708057 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708058 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708059 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708060 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708061 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1708062 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1708063 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1708064 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1708065 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1708066 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1708067 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1708068 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1708069 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1708070 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708071 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708072 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708073 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1708074 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708075 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708076 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708077 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708078 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708079 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708080 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708081 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708082 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708083 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708084 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708085 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708086 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1708087 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1708088 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1708089 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1708090 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1708091 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1708092 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1708093 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1708094 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1708095 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708096 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708097 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708098 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1708099 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708100 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708101 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708102 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708103 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708104 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708105 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708106 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708107 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708108 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708109 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708110 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708111 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1708112 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1708113 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1708114 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1708115 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1708116 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1708117 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1708118 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1708119 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1708120 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708121 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708122 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708123 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1708124 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708125 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708126 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708127 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708128 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708129 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708130 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708131 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708132 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708133 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708134 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708135 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708136 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1708137 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1708138 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1708139 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1708140 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1708141 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1708142 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1708143 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1708144 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1708145 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708146 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708147 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708148 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1708149 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708150 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708151 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708152 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708153 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708154 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708155 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708156 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708157 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708158 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708159 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708160 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708161 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1708162 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1708163 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1708164 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1708165 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1708166 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1708167 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1708168 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1708169 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1708170 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708171 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708172 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708173 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1708174 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708175 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708176 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708177 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708178 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708179 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708180 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708181 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708182 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708183 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708184 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708185 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708186 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1708187 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1708188 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1708189 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1708190 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1708191 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1708192 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1708193 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1708194 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1708195 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708196 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708197 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708198 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1708199 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708200 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708201 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708202 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708203 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708204 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708205 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708206 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708207 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708208 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708209 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708210 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708211 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1708212 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1708213 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1708214 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1708215 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1708216 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1708217 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1708218 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1708219 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1708220 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708221 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708222 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708223 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1708224 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708225 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708226 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708227 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708228 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708229 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708230 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708231 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708232 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708233 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708234 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708235 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708236 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1708237 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1708238 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1708239 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1708240 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1708241 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1708242 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1708243 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1708244 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1708245 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708246 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708247 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708248 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1708249 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708250 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708251 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708252 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708253 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708254 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708255 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708256 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708257 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708258 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708259 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708260 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708261 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1708262 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1708263 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1708264 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1708265 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1708266 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1708267 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1708268 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1708269 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1708270 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708271 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708272 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708273 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1708274 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708275 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708276 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708277 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708278 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708279 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708280 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708281 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708282 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708283 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708284 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708285 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708286 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1708287 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1708288 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1708289 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1708290 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1708291 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1708292 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1708293 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1708294 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1708295 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708296 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708297 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708298 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1708299 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708300 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708301 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708302 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708303 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708304 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708305 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708306 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708307 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708308 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708309 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708310 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708311 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1708312 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1708313 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1708314 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1708315 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1708316 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1708317 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1708318 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1708319 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1708320 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708321 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708322 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708323 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1708324 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708325 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708326 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708327 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708328 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708329 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708330 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708331 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708332 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708333 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708334 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708335 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708336 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1708337 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1708338 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1708339 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1708340 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1708341 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1708342 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1708343 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1708344 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1708345 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708346 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708347 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708348 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1708349 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708350 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708351 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708352 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708353 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708354 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708355 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708356 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708357 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708358 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708359 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708360 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708361 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1708362 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1708363 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1708364 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1708365 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1708366 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1708367 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1708368 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1708369 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1708370 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708371 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708372 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708373 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1708374 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708375 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708376 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708377 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708378 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708379 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708380 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708381 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708382 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708383 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708384 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708385 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708386 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1708387 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1708388 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1708389 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1708390 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1708391 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1708392 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1708393 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1708394 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1708395 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708396 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708397 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708398 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1708399 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708400 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708401 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708402 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708403 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708404 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708405 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708406 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708407 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708408 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708409 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708410 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708411 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1708412 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1708413 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1708414 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1708415 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1708416 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1708417 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1708418 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1708419 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1708420 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708421 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708422 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708423 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1708424 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708425 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708426 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708427 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708428 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708429 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708430 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708431 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708432 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708433 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708434 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708435 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708436 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1708437 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1708438 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1708439 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1708440 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1708441 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1708442 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1708443 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1708444 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1708445 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708446 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708447 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708448 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1708449 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708450 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708451 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708452 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708453 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708454 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708455 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708456 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708457 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708458 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708459 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708460 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708461 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1708462 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1708463 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1708464 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1708465 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1708466 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1708467 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1708468 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1708469 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1708470 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708471 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708472 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708473 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1708474 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708475 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708476 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708477 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708478 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708479 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708480 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708481 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708482 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708483 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708484 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708485 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708486 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1708487 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1708488 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1708489 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1708490 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1708491 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1708492 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1708493 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1708494 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1708495 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708496 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708497 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708498 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1708499 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708500 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708501 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708502 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708503 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708504 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708505 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708506 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708507 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708508 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708509 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708510 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708511 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1708512 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1708513 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1708514 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1708515 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1708516 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1708517 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1708518 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1708519 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1708520 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708521 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708522 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708523 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1708524 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708525 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708526 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708527 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708528 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708529 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708530 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708531 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708532 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708533 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708534 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708535 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708536 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1708537 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1708538 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1708539 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1708540 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1708541 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1708542 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1708543 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1708544 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1708545 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708546 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708547 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708548 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1708549 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708550 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708551 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708552 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708553 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708554 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708555 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708556 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708557 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708558 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708559 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708560 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708561 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1708562 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1708563 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1708564 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1708565 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1708566 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1708567 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1708568 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1708569 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1708570 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708571 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708572 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708573 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1708574 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708575 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708576 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708577 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708578 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708579 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708580 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708581 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708582 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708583 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708584 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708585 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708586 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1708587 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1708588 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1708589 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1708590 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1708591 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1708592 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1708593 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1708594 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1708595 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708596 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708597 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708598 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1708599 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708600 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708601 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708602 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708603 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708604 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708605 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708606 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708607 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708608 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708609 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708610 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708611 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1708612 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1708613 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1708614 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1708615 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1708616 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1708617 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1708618 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1708619 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1708620 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708621 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708622 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708623 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1708624 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708625 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708626 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708627 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708628 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708629 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708630 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708631 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708632 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708633 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708634 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708635 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708636 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1708637 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1708638 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1708639 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1708640 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1708641 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1708642 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1708643 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1708644 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1708645 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708646 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708647 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708648 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1708649 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708650 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708651 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708652 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708653 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708654 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708655 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708656 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708657 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708658 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708659 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708660 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708661 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1708662 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1708663 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1708664 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1708665 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1708666 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1708667 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1708668 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1708669 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1708670 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708671 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708672 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708673 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1708674 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708675 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708676 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708677 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708678 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708679 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708680 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708681 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708682 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708683 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708684 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708685 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708686 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1708687 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1708688 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1708689 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1708690 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1708691 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1708692 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1708693 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1708694 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1708695 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708696 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708697 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708698 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1708699 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708700 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708701 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708702 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708703 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708704 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708705 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708706 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708707 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708708 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708709 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708710 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708711 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1708712 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1708713 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1708714 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1708715 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1708716 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1708717 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1708718 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1708719 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1708720 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708721 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708722 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708723 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1708724 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708725 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708726 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708727 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708728 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708729 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708730 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708731 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708732 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708733 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708734 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708735 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708736 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1708737 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1708738 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1708739 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1708740 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1708741 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1708742 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1708743 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1708744 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1708745 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708746 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708747 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708748 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1708749 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708750 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708751 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708752 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708753 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708754 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708755 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708756 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708757 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708758 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708759 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708760 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708761 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1708762 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1708763 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1708764 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1708765 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1708766 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1708767 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1708768 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1708769 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1708770 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708771 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708772 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708773 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1708774 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708775 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708776 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708777 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708778 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708779 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708780 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708781 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708782 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708783 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708784 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708785 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708786 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1708787 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1708788 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1708789 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1708790 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1708791 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1708792 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1708793 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1708794 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1708795 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708796 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708797 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708798 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1708799 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708800 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708801 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708802 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708803 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708804 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708805 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708806 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708807 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708808 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708809 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708810 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708811 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1708812 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1708813 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1708814 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1708815 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1708816 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1708817 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1708818 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1708819 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1708820 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708821 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708822 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708823 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1708824 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708825 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708826 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708827 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708828 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708829 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708830 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708831 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708832 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708833 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708834 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708835 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708836 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1708837 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1708838 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1708839 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1708840 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1708841 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1708842 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1708843 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1708844 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1708845 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708846 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708847 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708848 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1708849 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708850 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708851 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708852 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708853 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708854 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708855 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708856 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708857 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708858 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708859 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708860 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708861 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1708862 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1708863 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1708864 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1708865 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1708866 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1708867 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1708868 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1708869 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1708870 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708871 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708872 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708873 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1708874 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708875 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708876 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708877 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708878 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708879 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708880 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708881 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708882 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708883 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708884 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708885 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708886 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1708887 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1708888 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1708889 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1708890 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1708891 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1708892 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1708893 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1708894 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1708895 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708896 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708897 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708898 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1708899 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708900 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708901 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708902 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708903 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708904 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708905 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708906 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708907 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708908 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708909 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708910 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708911 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1708912 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1708913 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1708914 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1708915 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1708916 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1708917 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1708918 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1708919 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1708920 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708921 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708922 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708923 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1708924 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708925 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708926 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708927 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708928 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708929 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708930 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708931 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708932 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708933 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708934 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708935 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708936 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1708937 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1708938 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1708939 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1708940 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1708941 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1708942 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1708943 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1708944 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1708945 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708946 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708947 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708948 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1708949 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708950 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708951 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708952 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708953 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708954 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708955 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708956 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708957 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708958 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708959 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708960 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708961 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1708962 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1708963 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1708964 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1708965 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1708966 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1708967 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1708968 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1708969 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1708970 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708971 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708972 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708973 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1708974 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708975 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708976 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708977 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708978 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708979 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708980 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708981 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708982 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708983 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708984 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708985 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708986 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1708987 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1708988 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1708989 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1708990 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1708991 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1708992 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1708993 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1708994 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1708995 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708996 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708997 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1708998 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1708999 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709000 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709001 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709002 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709003 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709004 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709005 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709006 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709007 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709008 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709009 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709010 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709011 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1709012 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1709013 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1709014 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1709015 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1709016 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1709017 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1709018 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1709019 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1709020 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709021 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709022 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709023 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1709024 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709025 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709026 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709027 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709028 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709029 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709030 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709031 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709032 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709033 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709034 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709035 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709036 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1709037 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1709038 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1709039 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1709040 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1709041 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1709042 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1709043 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1709044 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1709045 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709046 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709047 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709048 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1709049 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709050 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709051 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709052 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709053 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709054 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709055 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709056 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709057 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709058 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709059 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709060 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709061 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1709062 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1709063 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1709064 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1709065 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1709066 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1709067 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1709068 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1709069 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1709070 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709071 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709072 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709073 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1709074 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709075 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709076 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709077 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709078 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709079 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709080 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709081 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709082 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709083 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709084 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709085 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709086 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1709087 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1709088 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1709089 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1709090 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1709091 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1709092 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1709093 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1709094 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1709095 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709096 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709097 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709098 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1709099 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709100 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709101 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709102 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709103 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709104 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709105 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709106 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709107 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709108 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709109 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709110 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709111 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1709112 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1709113 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1709114 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1709115 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1709116 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1709117 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1709118 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1709119 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1709120 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709121 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709122 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709123 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1709124 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709125 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709126 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709127 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709128 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709129 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709130 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709131 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709132 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709133 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709134 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709135 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709136 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1709137 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1709138 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1709139 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1709140 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1709141 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1709142 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1709143 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1709144 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1709145 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709146 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709147 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709148 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1709149 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709150 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709151 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709152 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709153 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709154 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709155 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709156 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709157 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709158 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709159 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709160 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709161 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1709162 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1709163 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1709164 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1709165 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1709166 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1709167 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1709168 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1709169 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1709170 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709171 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709172 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709173 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1709174 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709175 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709176 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709177 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709178 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709179 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709180 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709181 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709182 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709183 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709184 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709185 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709186 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1709187 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1709188 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1709189 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1709190 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1709191 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1709192 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1709193 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1709194 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1709195 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709196 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709197 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709198 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1709199 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709200 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709201 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709202 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709203 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709204 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709205 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709206 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709207 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709208 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709209 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709210 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709211 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1709212 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1709213 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1709214 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1709215 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1709216 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1709217 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1709218 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1709219 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1709220 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709221 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709222 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709223 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1709224 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709225 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709226 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709227 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709228 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709229 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709230 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709231 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709232 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709233 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709234 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709235 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709236 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1709237 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1709238 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1709239 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1709240 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1709241 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1709242 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1709243 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1709244 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1709245 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709246 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709247 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709248 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1709249 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709250 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709251 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709252 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709253 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709254 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709255 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709256 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709257 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709258 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709259 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709260 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709261 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1709262 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1709263 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1709264 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1709265 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1709266 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1709267 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1709268 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1709269 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1709270 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709271 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709272 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709273 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1709274 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709275 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709276 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709277 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709278 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709279 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709280 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709281 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709282 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709283 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709284 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709285 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709286 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1709287 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1709288 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1709289 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1709290 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1709291 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1709292 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1709293 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1709294 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1709295 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709296 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709297 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709298 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1709299 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709300 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709301 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709302 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709303 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709304 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709305 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709306 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709307 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709308 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709309 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709310 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709311 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1709312 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1709313 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1709314 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1709315 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1709316 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1709317 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1709318 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1709319 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1709320 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709321 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709322 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709323 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1709324 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709325 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709326 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709327 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709328 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709329 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709330 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709331 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709332 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709333 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709334 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709335 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709336 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1709337 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1709338 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1709339 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1709340 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1709341 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1709342 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1709343 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1709344 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1709345 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709346 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709347 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709348 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1709349 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709350 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709351 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709352 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709353 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709354 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709355 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709356 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709357 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709358 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709359 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709360 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709361 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1709362 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1709363 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1709364 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1709365 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1709366 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1709367 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1709368 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1709369 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1709370 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709371 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709372 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709373 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1709374 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709375 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709376 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709377 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709378 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709379 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709380 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709381 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709382 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709383 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709384 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709385 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709386 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1709387 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1709388 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1709389 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1709390 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1709391 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1709392 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1709393 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1709394 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1709395 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709396 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709397 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709398 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1709399 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709400 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709401 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709402 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709403 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709404 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709405 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709406 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709407 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709408 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709409 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709410 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709411 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1709412 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1709413 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1709414 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1709415 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1709416 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1709417 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1709418 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1709419 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1709420 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709421 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709422 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709423 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1709424 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709425 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709426 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709427 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709428 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709429 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709430 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709431 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709432 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709433 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709434 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709435 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709436 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1709437 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1709438 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1709439 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1709440 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1709441 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1709442 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1709443 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1709444 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1709445 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709446 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709447 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709448 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1709449 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709450 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709451 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709452 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709453 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709454 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709455 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709456 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709457 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709458 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709459 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709460 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709461 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1709462 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1709463 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1709464 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1709465 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1709466 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1709467 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1709468 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1709469 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1709470 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709471 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709472 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709473 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1709474 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709475 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709476 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709477 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709478 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709479 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709480 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709481 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709482 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709483 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709484 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709485 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709486 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1709487 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1709488 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1709489 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1709490 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1709491 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1709492 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1709493 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1709494 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1709495 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709496 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709497 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709498 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1709499 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709500 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709501 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709502 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709503 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709504 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709505 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709506 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709507 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709508 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709509 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709510 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709511 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1709512 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1709513 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1709514 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1709515 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1709516 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1709517 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1709518 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1709519 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1709520 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709521 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709522 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709523 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1709524 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709525 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709526 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709527 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709528 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709529 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709530 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709531 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709532 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709533 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709534 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709535 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709536 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1709537 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1709538 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1709539 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1709540 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1709541 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1709542 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1709543 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1709544 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1709545 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709546 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709547 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709548 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1709549 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709550 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709551 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709552 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709553 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709554 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709555 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709556 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709557 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709558 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709559 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709560 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709561 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1709562 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1709563 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1709564 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1709565 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1709566 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1709567 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1709568 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1709569 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1709570 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709571 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709572 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709573 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1709574 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709575 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709576 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709577 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709578 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709579 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709580 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709581 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709582 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709583 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709584 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709585 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709586 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1709587 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1709588 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1709589 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1709590 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1709591 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1709592 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1709593 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1709594 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1709595 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709596 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709597 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709598 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1709599 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709600 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709601 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709602 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709603 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709604 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709605 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709606 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709607 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709608 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709609 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709610 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709611 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1709612 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1709613 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1709614 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1709615 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1709616 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1709617 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1709618 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1709619 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1709620 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709621 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709622 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709623 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1709624 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709625 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709626 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709627 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709628 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709629 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709630 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709631 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709632 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709633 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709634 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709635 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709636 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1709637 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1709638 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1709639 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1709640 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1709641 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1709642 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1709643 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1709644 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1709645 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709646 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709647 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709648 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1709649 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709650 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709651 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709652 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709653 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709654 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709655 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709656 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709657 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709658 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709659 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709660 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709661 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1709662 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1709663 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1709664 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1709665 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1709666 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1709667 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1709668 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1709669 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1709670 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709671 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709672 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709673 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1709674 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709675 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709676 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709677 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709678 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709679 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709680 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709681 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709682 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709683 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709684 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709685 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709686 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1709687 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1709688 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1709689 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1709690 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1709691 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1709692 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1709693 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1709694 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1709695 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709696 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709697 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709698 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1709699 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709700 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709701 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709702 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709703 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709704 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709705 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709706 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709707 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709708 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709709 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709710 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709711 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1709712 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1709713 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1709714 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1709715 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1709716 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1709717 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1709718 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1709719 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1709720 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709721 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709722 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709723 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1709724 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709725 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709726 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709727 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709728 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709729 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709730 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709731 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709732 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709733 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709734 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709735 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709736 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1709737 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1709738 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1709739 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1709740 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1709741 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1709742 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1709743 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1709744 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1709745 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709746 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709747 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709748 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1709749 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709750 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709751 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709752 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709753 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709754 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709755 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709756 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709757 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709758 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709759 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709760 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709761 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1709762 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1709763 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1709764 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1709765 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1709766 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1709767 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1709768 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1709769 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1709770 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709771 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709772 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709773 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1709774 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709775 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709776 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709777 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709778 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709779 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709780 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709781 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709782 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709783 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709784 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709785 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709786 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1709787 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1709788 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1709789 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1709790 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1709791 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1709792 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1709793 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1709794 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1709795 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709796 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709797 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709798 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1709799 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709800 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709801 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709802 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709803 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709804 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709805 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709806 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709807 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709808 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709809 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709810 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709811 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1709812 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1709813 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1709814 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1709815 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1709816 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1709817 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1709818 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1709819 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1709820 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709821 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709822 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709823 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1709824 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709825 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709826 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709827 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709828 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709829 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709830 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709831 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709832 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709833 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709834 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709835 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709836 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1709837 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1709838 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1709839 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1709840 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1709841 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1709842 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1709843 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1709844 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1709845 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709846 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709847 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709848 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1709849 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709850 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709851 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709852 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709853 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709854 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709855 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709856 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709857 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709858 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709859 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709860 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709861 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1709862 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1709863 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1709864 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1709865 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1709866 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1709867 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1709868 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1709869 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1709870 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709871 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709872 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709873 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1709874 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709875 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709876 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709877 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709878 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709879 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709880 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709881 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709882 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709883 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709884 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709885 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709886 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1709887 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1709888 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1709889 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1709890 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1709891 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1709892 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1709893 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1709894 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1709895 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709896 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709897 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709898 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1709899 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709900 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709901 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709902 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709903 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709904 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709905 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709906 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709907 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709908 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709909 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709910 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709911 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1709912 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1709913 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1709914 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1709915 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1709916 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1709917 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1709918 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1709919 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1709920 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709921 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709922 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709923 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1709924 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709925 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709926 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709927 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709928 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709929 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709930 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709931 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709932 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709933 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709934 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709935 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709936 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1709937 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1709938 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1709939 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1709940 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1709941 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1709942 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1709943 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1709944 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1709945 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709946 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709947 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709948 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1709949 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709950 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709951 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709952 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709953 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709954 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709955 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709956 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709957 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709958 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709959 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709960 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709961 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1709962 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1709963 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1709964 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1709965 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1709966 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1709967 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1709968 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1709969 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1709970 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709971 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709972 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709973 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1709974 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709975 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709976 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709977 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709978 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709979 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709980 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709981 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709982 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709983 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709984 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709985 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709986 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1709987 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1709988 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1709989 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1709990 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1709991 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1709992 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1709993 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1709994 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1709995 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709996 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709997 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1709998 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1709999 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710000 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710001 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710002 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710003 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710004 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710005 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710006 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710007 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710008 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710009 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710010 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710011 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1710012 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1710013 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1710014 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1710015 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1710016 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1710017 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1710018 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1710019 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1710020 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710021 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710022 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710023 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1710024 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710025 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710026 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710027 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710028 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710029 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710030 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710031 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710032 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710033 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710034 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710035 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710036 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1710037 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1710038 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1710039 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1710040 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1710041 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1710042 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1710043 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1710044 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1710045 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710046 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710047 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710048 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1710049 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710050 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710051 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710052 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710053 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710054 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710055 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710056 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710057 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710058 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710059 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710060 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710061 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1710062 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1710063 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1710064 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1710065 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1710066 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1710067 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1710068 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1710069 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1710070 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710071 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710072 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710073 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1710074 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710075 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710076 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710077 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710078 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710079 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710080 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710081 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710082 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710083 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710084 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710085 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710086 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1710087 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1710088 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1710089 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1710090 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1710091 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1710092 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1710093 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1710094 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1710095 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710096 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710097 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710098 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1710099 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710100 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710101 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710102 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710103 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710104 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710105 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710106 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710107 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710108 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710109 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710110 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710111 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1710112 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1710113 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1710114 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1710115 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1710116 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1710117 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1710118 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1710119 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1710120 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710121 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710122 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710123 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1710124 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710125 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710126 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710127 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710128 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710129 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710130 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710131 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710132 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710133 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710134 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710135 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710136 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1710137 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1710138 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1710139 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1710140 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1710141 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1710142 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1710143 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1710144 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1710145 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710146 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710147 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710148 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1710149 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710150 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710151 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710152 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710153 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710154 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710155 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710156 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710157 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710158 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710159 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710160 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710161 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1710162 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1710163 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1710164 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1710165 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1710166 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1710167 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1710168 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1710169 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1710170 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710171 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710172 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710173 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1710174 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710175 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710176 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710177 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710178 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710179 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710180 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710181 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710182 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710183 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710184 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710185 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710186 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1710187 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1710188 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1710189 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1710190 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1710191 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1710192 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1710193 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1710194 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1710195 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710196 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710197 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710198 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1710199 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710200 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710201 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710202 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710203 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710204 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710205 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710206 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710207 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710208 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710209 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710210 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710211 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1710212 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1710213 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1710214 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1710215 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1710216 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1710217 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1710218 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1710219 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1710220 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710221 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710222 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710223 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1710224 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710225 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710226 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710227 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710228 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710229 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710230 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710231 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710232 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710233 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710234 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710235 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710236 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1710237 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1710238 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1710239 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1710240 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1710241 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1710242 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1710243 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1710244 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1710245 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710246 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710247 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710248 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1710249 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710250 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710251 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710252 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710253 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710254 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710255 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710256 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710257 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710258 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710259 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710260 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710261 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1710262 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1710263 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1710264 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1710265 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1710266 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1710267 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1710268 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1710269 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1710270 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710271 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710272 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710273 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1710274 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710275 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710276 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710277 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710278 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710279 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710280 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710281 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710282 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710283 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710284 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710285 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710286 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1710287 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1710288 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1710289 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1710290 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1710291 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1710292 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1710293 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1710294 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1710295 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710296 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710297 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710298 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1710299 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710300 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710301 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710302 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710303 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710304 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710305 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710306 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710307 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710308 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710309 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710310 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710311 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1710312 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1710313 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1710314 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1710315 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1710316 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1710317 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1710318 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1710319 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1710320 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710321 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710322 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710323 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1710324 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710325 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710326 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710327 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710328 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710329 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710330 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710331 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710332 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710333 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710334 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710335 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710336 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1710337 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1710338 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1710339 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1710340 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1710341 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1710342 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1710343 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1710344 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1710345 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710346 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710347 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710348 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1710349 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710350 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710351 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710352 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710353 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710354 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710355 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710356 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710357 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710358 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710359 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710360 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710361 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1710362 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1710363 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1710364 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1710365 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1710366 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1710367 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1710368 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1710369 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1710370 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710371 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710372 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710373 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1710374 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710375 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710376 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710377 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710378 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710379 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710380 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710381 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710382 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710383 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710384 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710385 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710386 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1710387 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1710388 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1710389 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1710390 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1710391 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1710392 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1710393 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1710394 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1710395 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710396 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710397 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710398 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1710399 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710400 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710401 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710402 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710403 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710404 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710405 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710406 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710407 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710408 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710409 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710410 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710411 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1710412 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1710413 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1710414 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1710415 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1710416 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1710417 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1710418 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1710419 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1710420 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710421 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710422 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710423 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1710424 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710425 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710426 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710427 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710428 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710429 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710430 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710431 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710432 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710433 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710434 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710435 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710436 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1710437 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1710438 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1710439 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1710440 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1710441 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1710442 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1710443 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1710444 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1710445 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710446 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710447 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710448 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1710449 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710450 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710451 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710452 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710453 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710454 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710455 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710456 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710457 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710458 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710459 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710460 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710461 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1710462 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1710463 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1710464 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1710465 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1710466 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1710467 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1710468 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1710469 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1710470 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710471 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710472 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710473 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1710474 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710475 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710476 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710477 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710478 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710479 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710480 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710481 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710482 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710483 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710484 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710485 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710486 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1710487 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1710488 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1710489 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1710490 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1710491 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1710492 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1710493 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1710494 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1710495 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710496 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710497 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710498 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1710499 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710500 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710501 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710502 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710503 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710504 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710505 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710506 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710507 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710508 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710509 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710510 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710511 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1710512 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1710513 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1710514 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1710515 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1710516 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1710517 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1710518 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1710519 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1710520 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710521 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710522 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710523 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1710524 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710525 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710526 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710527 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710528 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710529 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710530 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710531 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710532 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710533 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710534 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710535 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710536 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1710537 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1710538 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1710539 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1710540 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1710541 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1710542 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1710543 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1710544 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1710545 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710546 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710547 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710548 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1710549 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710550 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710551 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710552 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710553 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710554 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710555 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710556 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710557 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710558 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710559 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710560 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710561 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1710562 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1710563 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1710564 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1710565 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1710566 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1710567 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1710568 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1710569 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1710570 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710571 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710572 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710573 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1710574 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710575 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710576 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710577 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710578 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710579 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710580 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710581 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710582 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710583 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710584 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710585 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710586 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1710587 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1710588 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1710589 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1710590 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1710591 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1710592 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1710593 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1710594 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1710595 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710596 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710597 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710598 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1710599 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710600 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710601 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710602 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710603 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710604 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710605 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710606 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710607 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710608 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710609 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710610 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710611 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1710612 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1710613 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1710614 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1710615 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1710616 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1710617 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1710618 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1710619 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1710620 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710621 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710622 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710623 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1710624 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710625 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710626 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710627 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710628 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710629 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710630 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710631 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710632 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710633 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710634 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710635 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710636 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1710637 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1710638 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1710639 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1710640 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1710641 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1710642 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1710643 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1710644 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1710645 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710646 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710647 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710648 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1710649 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710650 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710651 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710652 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710653 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710654 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710655 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710656 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710657 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710658 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710659 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710660 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710661 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1710662 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1710663 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1710664 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1710665 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1710666 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1710667 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1710668 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1710669 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1710670 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710671 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710672 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710673 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1710674 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710675 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710676 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710677 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710678 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710679 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710680 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710681 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710682 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710683 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710684 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710685 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710686 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1710687 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1710688 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1710689 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1710690 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1710691 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1710692 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1710693 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1710694 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1710695 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710696 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710697 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710698 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1710699 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710700 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710701 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710702 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710703 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710704 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710705 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710706 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710707 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710708 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710709 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710710 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710711 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1710712 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1710713 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1710714 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1710715 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1710716 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1710717 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1710718 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1710719 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1710720 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710721 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710722 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710723 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1710724 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710725 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710726 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710727 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710728 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710729 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710730 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710731 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710732 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710733 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710734 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710735 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710736 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1710737 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1710738 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1710739 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1710740 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1710741 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1710742 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1710743 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1710744 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1710745 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710746 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710747 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710748 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1710749 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710750 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710751 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710752 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710753 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710754 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710755 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710756 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710757 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710758 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710759 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710760 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710761 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1710762 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1710763 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1710764 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1710765 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1710766 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1710767 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1710768 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1710769 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1710770 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710771 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710772 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710773 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1710774 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710775 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710776 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710777 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710778 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710779 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710780 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710781 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710782 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710783 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710784 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710785 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710786 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1710787 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1710788 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1710789 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1710790 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1710791 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1710792 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1710793 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1710794 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1710795 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710796 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710797 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710798 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1710799 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710800 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710801 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710802 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710803 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710804 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710805 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710806 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710807 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710808 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710809 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710810 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710811 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1710812 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1710813 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1710814 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1710815 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1710816 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1710817 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1710818 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1710819 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1710820 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710821 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710822 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710823 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1710824 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710825 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710826 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710827 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710828 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710829 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710830 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710831 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710832 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710833 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710834 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710835 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710836 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1710837 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1710838 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1710839 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1710840 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1710841 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1710842 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1710843 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1710844 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1710845 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710846 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710847 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710848 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1710849 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710850 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710851 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710852 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710853 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710854 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710855 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710856 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710857 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710858 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710859 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710860 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710861 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1710862 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1710863 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1710864 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1710865 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1710866 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1710867 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1710868 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1710869 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1710870 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710871 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710872 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710873 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1710874 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710875 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710876 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710877 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710878 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710879 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710880 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710881 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710882 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710883 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710884 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710885 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710886 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1710887 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1710888 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1710889 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1710890 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1710891 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1710892 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1710893 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1710894 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1710895 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710896 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710897 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710898 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1710899 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710900 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710901 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710902 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710903 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710904 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710905 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710906 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710907 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710908 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710909 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710910 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710911 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1710912 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1710913 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1710914 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1710915 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1710916 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1710917 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1710918 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1710919 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1710920 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710921 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710922 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710923 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1710924 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710925 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710926 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710927 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710928 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710929 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710930 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710931 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710932 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710933 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710934 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710935 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710936 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1710937 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1710938 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1710939 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1710940 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1710941 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1710942 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1710943 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1710944 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1710945 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710946 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710947 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710948 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1710949 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710950 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710951 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710952 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710953 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710954 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710955 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710956 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710957 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710958 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710959 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710960 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710961 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1710962 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1710963 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1710964 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1710965 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1710966 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1710967 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1710968 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1710969 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1710970 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710971 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710972 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710973 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1710974 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710975 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710976 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710977 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710978 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710979 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710980 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710981 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710982 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710983 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710984 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710985 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710986 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1710987 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1710988 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1710989 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1710990 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1710991 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1710992 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1710993 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1710994 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1710995 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710996 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710997 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1710998 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1710999 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711000 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711001 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711002 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711003 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711004 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711005 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711006 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711007 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711008 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711009 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711010 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711011 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1711012 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1711013 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1711014 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1711015 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1711016 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1711017 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1711018 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1711019 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1711020 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711021 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711022 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711023 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1711024 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711025 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711026 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711027 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711028 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711029 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711030 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711031 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711032 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711033 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711034 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711035 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711036 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1711037 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1711038 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1711039 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1711040 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1711041 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1711042 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1711043 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1711044 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1711045 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711046 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711047 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711048 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1711049 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711050 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711051 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711052 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711053 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711054 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711055 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711056 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711057 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711058 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711059 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711060 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711061 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1711062 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1711063 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1711064 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1711065 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1711066 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1711067 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1711068 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1711069 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1711070 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711071 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711072 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711073 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1711074 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711075 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711076 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711077 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711078 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711079 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711080 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711081 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711082 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711083 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711084 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711085 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711086 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1711087 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1711088 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1711089 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1711090 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1711091 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1711092 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1711093 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1711094 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1711095 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711096 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711097 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711098 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1711099 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711100 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711101 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711102 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711103 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711104 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711105 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711106 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711107 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711108 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711109 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711110 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711111 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1711112 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1711113 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1711114 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1711115 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1711116 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1711117 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1711118 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1711119 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1711120 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711121 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711122 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711123 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1711124 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711125 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711126 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711127 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711128 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711129 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711130 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711131 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711132 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711133 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711134 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711135 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711136 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1711137 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1711138 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1711139 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1711140 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1711141 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1711142 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1711143 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1711144 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1711145 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711146 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711147 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711148 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1711149 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711150 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711151 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711152 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711153 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711154 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711155 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711156 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711157 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711158 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711159 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711160 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711161 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1711162 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1711163 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1711164 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1711165 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1711166 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1711167 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1711168 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1711169 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1711170 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711171 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711172 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711173 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1711174 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711175 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711176 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711177 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711178 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711179 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711180 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711181 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711182 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711183 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711184 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711185 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711186 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1711187 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1711188 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1711189 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1711190 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1711191 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1711192 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1711193 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1711194 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1711195 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711196 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711197 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711198 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1711199 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711200 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711201 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711202 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711203 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711204 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711205 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711206 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711207 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711208 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711209 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711210 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711211 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1711212 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1711213 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1711214 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1711215 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1711216 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1711217 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1711218 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1711219 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1711220 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711221 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711222 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711223 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1711224 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711225 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711226 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711227 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711228 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711229 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711230 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711231 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711232 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711233 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711234 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711235 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711236 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1711237 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1711238 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1711239 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1711240 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1711241 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1711242 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1711243 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1711244 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1711245 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711246 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711247 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711248 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1711249 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711250 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711251 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711252 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711253 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711254 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711255 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711256 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711257 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711258 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711259 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711260 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711261 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1711262 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1711263 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1711264 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1711265 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1711266 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1711267 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1711268 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1711269 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1711270 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711271 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711272 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711273 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1711274 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711275 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711276 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711277 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711278 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711279 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711280 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711281 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711282 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711283 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711284 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711285 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711286 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1711287 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1711288 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1711289 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1711290 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1711291 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1711292 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1711293 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1711294 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1711295 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711296 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711297 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711298 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1711299 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711300 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711301 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711302 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711303 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711304 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711305 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711306 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711307 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711308 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711309 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711310 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711311 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1711312 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1711313 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1711314 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1711315 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1711316 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1711317 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1711318 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1711319 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1711320 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711321 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711322 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711323 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1711324 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711325 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711326 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711327 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711328 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711329 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711330 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711331 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711332 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711333 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711334 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711335 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711336 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1711337 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1711338 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1711339 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1711340 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1711341 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1711342 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1711343 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1711344 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1711345 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711346 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711347 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711348 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1711349 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711350 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711351 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711352 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711353 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711354 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_MISS> ITLB miss / VADDR = 0x800013c4 / BYPASS = 0x1 / PTE_ADR = 0x000019008
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711355 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3.DCACHE_TLB_PTE2_GET> HIT in dcache: PTE_FLAGS = 0x8a000000 PTE_PPN = 0x5
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711356 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB: way = 0 / set = 1
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711357 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_PTE2_UPDT> L/R bit update required
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711358 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711359 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711360 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711361 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_IDLE> Receive command from srcid 0d3 / for address 0x000019008
****************** cycle 1711362 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x08a000000 be = 0x0f plen = 0d8
****************** cycle 1711363 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_CAS | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_CMD_CAS> Pushing command into cmd_cas_fifo: address = 0x000019008 srcid = 0d3 trdid = 0d0 pktid = 0d5 wdata = 0x0aa000000 be = 0x0f plen = 0d8
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0x8a000000 eop = 0 cpt  = 0
****************** cycle 1711364 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_IDLE> CAS command:  srcid = 3 addr = 0x19008 wdata = 0xaa000000 eop = 1 cpt  = 1
****************** cycle 1711365 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_REQ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_REQ> Requesting DIR lock 
****************** cycle 1711366 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_LOCK | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_LOCK> Directory acces / address = 0x19008 / hit = 1 / count = 3 / is_cnt = 0
****************** cycle 1711367 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_READ | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_READ> Read data from  cache and store it in buffer
****************** cycle 1711368 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_DIR_HIT_COMPARE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_DIR_HIT_COMPARE> Compare the old and the new data / expected value = 0x8a000000 / actual value = 0xaa000000 / forced_fail = 0
****************** cycle 1711369 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_RSP_FAIL | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.CAS_RSP_FAIL> Request TGT_RSP to send a failure response
****************** cycle 1711370 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711371 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711372 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711373 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
  <MEMC memc_0_0.TGT_RSP_CAS> CAS response / rsrcid = 3 / rtrdid = 0 / rpktid = 5
****************** cycle 1711374 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_LR_WAIT> SC response received
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711375 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 DCACHE_TLB_RETURN> TLB MISS completed
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711376 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711377 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711378 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
  <PROC proc_0_0_2 r_cc_receive_dcache_req = 0x1
  <PROC proc_0_0_2 r_dcache_miss_inval = 0
  <PROC proc_0_0_3 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_3 r_dcache_miss_inval = 0
****************** cycle 1711379 ************************************************
PROC proc_0_0_2
  <InsReq    valid mode MODE_KERNEL @ 0x80090008>
  <InsRsp    valid no error ins 0xafbe0060>
  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xbfc0b2fc wdata 0 be 0xf>
  <DataRsp invalid no error rdata 0>
  ICACHE_IDLE | DCACHE_TLB_PTE2_GET | CMD_IDLE | RSP_IDLE | CC_RECEIVE_IDLE | CC_SEND_IDLE
MEMC memc_0_0
  TGT_CMD_IDLE | TGT_RSP_CAS_IDLE | READ_IDLE | WRITE_IDLE | CAS_IDLE | CLEANUP_IDLE
  CC_SEND_CAS_UPDT_NLINE | CC_RECEIVE_IDLE | MULTI_ACK_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
  <PROC proc_0_0_1 r_cc_receive_dcache_req = 0
  <PROC proc_0_0_1 r_dcache_miss_inval = 0
ERROR in CC_VCACHE_WRAPPER proc_0_0_2
 stop at cycle 1711379
 frozen since cycle 1701379
proc_0_0_2 PC: 80090008 NPC: 8009000c Ins: afbe0060
 Cause.xcode: 0
 Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 400004
 op:  2b (sw)
 i rs: 1d rt: 1e i: 60
 r rs: 29 rt: 30 rd: 0 sh: 1 func: 20
 V rs: bfc0b298 rt: 0
  0: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
 24: 00000000 25: 00000000 26: 80090000 27: 0000000f 28: 00000000 29: bfc0b298 30: 00000000 31: 00000000